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This adds location info for all llvm_unreachable calls (which is a macro now) in !NDEBUG builds. In NDEBUG builds location info and the message is off (it only prints "UREACHABLE executed"). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75640 91177308-0d34-0410-b5e6-96231b3b80d8
198 lines
6.7 KiB
C++
198 lines
6.7 KiB
C++
//===- SparcRegisterInfo.cpp - SPARC Register Information -------*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains the SPARC implementation of the TargetRegisterInfo class.
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//
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//===----------------------------------------------------------------------===//
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#include "Sparc.h"
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#include "SparcRegisterInfo.h"
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#include "SparcSubtarget.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/CodeGen/MachineFrameInfo.h"
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#include "llvm/CodeGen/MachineLocation.h"
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#include "llvm/Support/ErrorHandling.h"
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#include "llvm/Target/TargetInstrInfo.h"
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#include "llvm/Type.h"
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#include "llvm/ADT/BitVector.h"
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#include "llvm/ADT/STLExtras.h"
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using namespace llvm;
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SparcRegisterInfo::SparcRegisterInfo(SparcSubtarget &st,
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const TargetInstrInfo &tii)
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: SparcGenRegisterInfo(SP::ADJCALLSTACKDOWN, SP::ADJCALLSTACKUP),
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Subtarget(st), TII(tii) {
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}
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const unsigned* SparcRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF)
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const {
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static const unsigned CalleeSavedRegs[] = { 0 };
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return CalleeSavedRegs;
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}
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BitVector SparcRegisterInfo::getReservedRegs(const MachineFunction &MF) const {
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BitVector Reserved(getNumRegs());
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Reserved.set(SP::G2);
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Reserved.set(SP::G3);
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Reserved.set(SP::G4);
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Reserved.set(SP::O6);
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Reserved.set(SP::I6);
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Reserved.set(SP::I7);
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Reserved.set(SP::G0);
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Reserved.set(SP::G5);
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Reserved.set(SP::G6);
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Reserved.set(SP::G7);
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return Reserved;
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}
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const TargetRegisterClass* const*
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SparcRegisterInfo::getCalleeSavedRegClasses(const MachineFunction *MF) const {
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static const TargetRegisterClass * const CalleeSavedRegClasses[] = { 0 };
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return CalleeSavedRegClasses;
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}
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bool SparcRegisterInfo::hasFP(const MachineFunction &MF) const {
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return false;
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}
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void SparcRegisterInfo::
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eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
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MachineBasicBlock::iterator I) const {
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MachineInstr &MI = *I;
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DebugLoc dl = MI.getDebugLoc();
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int Size = MI.getOperand(0).getImm();
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if (MI.getOpcode() == SP::ADJCALLSTACKDOWN)
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Size = -Size;
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if (Size)
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BuildMI(MBB, I, dl, TII.get(SP::ADDri), SP::O6).addReg(SP::O6).addImm(Size);
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MBB.erase(I);
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}
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void SparcRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
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int SPAdj, RegScavenger *RS) const {
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assert(SPAdj == 0 && "Unexpected");
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unsigned i = 0;
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MachineInstr &MI = *II;
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DebugLoc dl = MI.getDebugLoc();
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while (!MI.getOperand(i).isFI()) {
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++i;
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assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
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}
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int FrameIndex = MI.getOperand(i).getIndex();
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// Addressable stack objects are accessed using neg. offsets from %fp
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MachineFunction &MF = *MI.getParent()->getParent();
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int Offset = MF.getFrameInfo()->getObjectOffset(FrameIndex) +
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MI.getOperand(i+1).getImm();
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// Replace frame index with a frame pointer reference.
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if (Offset >= -4096 && Offset <= 4095) {
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// If the offset is small enough to fit in the immediate field, directly
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// encode it.
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MI.getOperand(i).ChangeToRegister(SP::I6, false);
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MI.getOperand(i+1).ChangeToImmediate(Offset);
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} else {
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// Otherwise, emit a G1 = SETHI %hi(offset). FIXME: it would be better to
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// scavenge a register here instead of reserving G1 all of the time.
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unsigned OffHi = (unsigned)Offset >> 10U;
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BuildMI(*MI.getParent(), II, dl, TII.get(SP::SETHIi), SP::G1).addImm(OffHi);
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// Emit G1 = G1 + I6
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BuildMI(*MI.getParent(), II, dl, TII.get(SP::ADDrr), SP::G1).addReg(SP::G1)
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.addReg(SP::I6);
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// Insert: G1+%lo(offset) into the user.
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MI.getOperand(i).ChangeToRegister(SP::G1, false);
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MI.getOperand(i+1).ChangeToImmediate(Offset & ((1 << 10)-1));
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}
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}
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void SparcRegisterInfo::
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processFunctionBeforeFrameFinalized(MachineFunction &MF) const {}
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void SparcRegisterInfo::emitPrologue(MachineFunction &MF) const {
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MachineBasicBlock &MBB = MF.front();
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MachineFrameInfo *MFI = MF.getFrameInfo();
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MachineBasicBlock::iterator MBBI = MBB.begin();
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DebugLoc dl = (MBBI != MBB.end() ?
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MBBI->getDebugLoc() : DebugLoc::getUnknownLoc());
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// Get the number of bytes to allocate from the FrameInfo
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int NumBytes = (int) MFI->getStackSize();
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// Emit the correct save instruction based on the number of bytes in
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// the frame. Minimum stack frame size according to V8 ABI is:
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// 16 words for register window spill
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// 1 word for address of returned aggregate-value
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// + 6 words for passing parameters on the stack
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// ----------
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// 23 words * 4 bytes per word = 92 bytes
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NumBytes += 92;
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// Round up to next doubleword boundary -- a double-word boundary
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// is required by the ABI.
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NumBytes = (NumBytes + 7) & ~7;
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NumBytes = -NumBytes;
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if (NumBytes >= -4096) {
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BuildMI(MBB, MBBI, dl, TII.get(SP::SAVEri), SP::O6)
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.addReg(SP::O6).addImm(NumBytes);
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} else {
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// Emit this the hard way. This clobbers G1 which we always know is
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// available here.
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unsigned OffHi = (unsigned)NumBytes >> 10U;
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BuildMI(MBB, MBBI, dl, TII.get(SP::SETHIi), SP::G1).addImm(OffHi);
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// Emit G1 = G1 + I6
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BuildMI(MBB, MBBI, dl, TII.get(SP::ORri), SP::G1)
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.addReg(SP::G1).addImm(NumBytes & ((1 << 10)-1));
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BuildMI(MBB, MBBI, dl, TII.get(SP::SAVErr), SP::O6)
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.addReg(SP::O6).addReg(SP::G1);
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}
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}
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void SparcRegisterInfo::emitEpilogue(MachineFunction &MF,
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MachineBasicBlock &MBB) const {
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MachineBasicBlock::iterator MBBI = prior(MBB.end());
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DebugLoc dl = MBBI->getDebugLoc();
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assert(MBBI->getOpcode() == SP::RETL &&
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"Can only put epilog before 'retl' instruction!");
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BuildMI(MBB, MBBI, dl, TII.get(SP::RESTORErr), SP::G0).addReg(SP::G0)
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.addReg(SP::G0);
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}
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unsigned SparcRegisterInfo::getRARegister() const {
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llvm_unreachable("What is the return address register");
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return 0;
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}
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unsigned SparcRegisterInfo::getFrameRegister(MachineFunction &MF) const {
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llvm_unreachable("What is the frame register");
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return SP::G1;
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}
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unsigned SparcRegisterInfo::getEHExceptionRegister() const {
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llvm_unreachable("What is the exception register");
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return 0;
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}
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unsigned SparcRegisterInfo::getEHHandlerRegister() const {
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llvm_unreachable("What is the exception handler register");
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return 0;
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}
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int SparcRegisterInfo::getDwarfRegNum(unsigned RegNum, bool isEH) const {
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llvm_unreachable("What is the dwarf register number");
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return -1;
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}
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#include "SparcGenRegisterInfo.inc"
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