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https://github.com/c64scene-ar/llvm-6502.git
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8239daf7c8
1. Fix pre-ra scheduler so it doesn't try to push instructions above calls to "optimize for latency". Call instructions don't have the right latency and this is more likely to use introduce spills. 2. Fix if-converter cost function. For ARM, it should use instruction latencies, not # of micro-ops since multi-latency instructions is completely executed even when the predicate is false. Also, some instruction will be "slower" when they are predicated due to the register def becoming implicit input. rdar://8598427 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118135 91177308-0d34-0410-b5e6-96231b3b80d8
44 lines
1.4 KiB
LLVM
44 lines
1.4 KiB
LLVM
; RUN: llc < %s -mtriple=arm-apple-darwin -mcpu=cortex-a9 | FileCheck %s
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; rdar://8402126
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; Make sure if-converter is not predicating vldmia and ldmia. These are
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; micro-coded and would have long issue latency even if predicated on
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; false predicate.
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define void @t(double %a, double %b, double %c, double %d, i32* nocapture %solutions, double* nocapture %x) nounwind {
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entry:
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; CHECK: t:
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; CHECK: vpop {d8}
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; CHECK-NOT: vpopne
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; CHECK: ldmia sp!, {r7, pc}
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; CHECK: vpop {d8}
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; CHECK: ldmia sp!, {r7, pc}
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br i1 undef, label %if.else, label %if.then
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if.then: ; preds = %entry
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%mul73 = fmul double undef, 0.000000e+00
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%sub76 = fsub double %mul73, undef
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store double %sub76, double* undef, align 4
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%call88 = tail call double @cos(double 0.000000e+00) nounwind
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%mul89 = fmul double undef, %call88
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%sub92 = fsub double %mul89, undef
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store double %sub92, double* undef, align 4
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ret void
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if.else: ; preds = %entry
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%tmp101 = tail call double @llvm.pow.f64(double undef, double 0x3FD5555555555555)
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%add112 = fadd double %tmp101, undef
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%mul118 = fmul double %add112, undef
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store double 0.000000e+00, double* %x, align 4
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ret void
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}
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declare double @acos(double)
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declare double @sqrt(double) readnone
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declare double @cos(double) readnone
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declare double @fabs(double)
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declare double @llvm.pow.f64(double, double) nounwind readonly
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