llvm-6502/test/CodeGen/X86/membarrier.ll
Eric Christopher 77ed1353bf Go ahead and emit the barrier on x86-64 even without sse2. The
processor supports it just fine.

Fixes PR9675 and rdar://9740801


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134664 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-08 00:04:56 +00:00

16 lines
512 B
LLVM

; RUN: llc < %s -march=x86-64 -mattr=-sse -O0
; PR9675
define i32 @t() {
entry:
%i = alloca i32, align 4
store i32 1, i32* %i, align 4
call void @llvm.memory.barrier(i1 true, i1 true, i1 true, i1 true, i1 true)
%0 = call i32 @llvm.atomic.load.sub.i32.p0i32(i32* %i, i32 1)
call void @llvm.memory.barrier(i1 true, i1 true, i1 true, i1 true, i1 true)
ret i32 0
}
declare i32 @llvm.atomic.load.sub.i32.p0i32(i32* nocapture, i32) nounwind
declare void @llvm.memory.barrier(i1, i1, i1, i1, i1) nounwind