llvm-6502/test/CodeGen
Ulrich Weigand 7e0334d096 [LegalizeVectorTypes] Allow single loads and stores for more short vectors
When lowering a load or store for TypeWidenVector, the type legalizer
would use a single load or store if the associated integer type was legal.
E.g. it would load a v4i8 as an i32 if i32 was legal.

This patch extends that behavior to promoted integers as well as legal ones.
If the integer type for the full vector width is TypePromoteInteger,
the element type is going to be TypePromoteInteger too, and it's still
better to use a single promoting load or truncating store rather than N
individual promoting loads or truncating stores.  E.g. if you have a v2i8
on a target where i16 is promoted to i32, it's better to load the v2i8 as
an i16 rather than load both i8s individually.

Original patch by Richard Sandiford.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@236528 91177308-0d34-0410-b5e6-96231b3b80d8
2015-05-05 19:32:57 +00:00
..
AArch64 [ShrinkWrap] Add (a simplified version) of shrink-wrapping. 2015-05-05 17:38:16 +00:00
ARM Revert "Fix IfConverter to handle regmask machine operands." 2015-05-05 18:49:05 +00:00
BPF [opaque pointer type] Add textual IR support for explicit type parameter to the call instruction 2015-04-16 23:24:18 +00:00
CPP [opaque pointer type] Add textual IR support for explicit type parameter to the call instruction 2015-04-16 23:24:18 +00:00
Generic [Hexagon] r236351 fix does not work on builder configurations yet. 2015-05-01 22:39:20 +00:00
Hexagon IR: Give 'DI' prefix to debug info metadata 2015-04-29 16:38:44 +00:00
Inputs IR: Give 'DI' prefix to debug info metadata 2015-04-29 16:38:44 +00:00
Mips [mips] Generate code for insert/extract operations when using the N64 ABI and MSA. 2015-05-05 10:32:24 +00:00
MSP430 [opaque pointer type] Add textual IR support for explicit type parameter to gep operator 2015-03-13 18:20:45 +00:00
NVPTX [NVPTX] Handle addrspacecast constant expressions in aggregate initializers 2015-04-28 17:18:30 +00:00
PowerPC This patch adds ABI support for v1i128 data type. 2015-05-05 16:10:44 +00:00
R600 R600/SI: Add VCC as an implict def of SI_KILL 2015-05-01 03:44:09 +00:00
SPARC [opaque pointer type] Add textual IR support for explicit type parameter to the call instruction 2015-04-16 23:24:18 +00:00
SystemZ [LegalizeVectorTypes] Allow single loads and stores for more short vectors 2015-05-05 19:32:57 +00:00
Thumb IR: Give 'DI' prefix to debug info metadata 2015-04-29 16:38:44 +00:00
Thumb2 Thumb2: When applying branch optimizations, visit branches in reverse order. 2015-04-23 20:31:35 +00:00
WinEH Flip r236172 testcase RUN option ordering for BSD sed(1). NFC. 2015-04-30 00:07:34 +00:00
X86 Re-land "[WinEH] Add an EH registration and state insertion pass for 32-bit x86" 2015-05-05 17:44:16 +00:00
XCore IR: Give 'DI' prefix to debug info metadata 2015-04-29 16:38:44 +00:00