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This fixes PEI as previously described, but correctly handles the case where the instruction defining the virtual register to be scavenged is the first in the block. Arnold provided me with a bugpoint-reduced test case, but even that seems too large to use as a regression test. If I'm successful in cleaning it up then I'll commit that as well. Original commit message: This change fixes a bug that I introduced in r178058. After a register is scavenged using one of the available spills slots the instruction defining the virtual register needs to be moved to after the spill code. The scavenger has already processed the defining instruction so that registers killed by that instruction are available for definition in that same instruction. Unfortunately, after this, the scavenger needs to iterate through the spill code and then visit, again, the instruction that defines the now-scavenged register. In order to avoid confusion, the register scavenger needs the ability to 'back up' through the spill code so that it can again process the instructions in the appropriate order. Prior to this fix, once the scavenger reached the just-moved instruction, it would assert if it killed any registers because, having already processed the instruction, it believed they were undefined. Unfortunately, I don't yet have a small test case. Thanks to Pranav Bhandarkar for diagnosing the problem and testing this fix. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178919 91177308-0d34-0410-b5e6-96231b3b80d8
209 lines
7.0 KiB
C++
209 lines
7.0 KiB
C++
//===-- RegisterScavenging.h - Machine register scavenging ------*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file declares the machine register scavenger class. It can provide
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// information such as unused register at any point in a machine basic block.
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// It also provides a mechanism to make registers availbale by evicting them
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// to spill slots.
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_CODEGEN_REGISTERSCAVENGING_H
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#define LLVM_CODEGEN_REGISTERSCAVENGING_H
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#include "llvm/ADT/BitVector.h"
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#include "llvm/CodeGen/MachineBasicBlock.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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namespace llvm {
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class MachineRegisterInfo;
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class TargetRegisterInfo;
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class TargetInstrInfo;
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class TargetRegisterClass;
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class RegScavenger {
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const TargetRegisterInfo *TRI;
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const TargetInstrInfo *TII;
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MachineRegisterInfo* MRI;
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MachineBasicBlock *MBB;
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MachineBasicBlock::iterator MBBI;
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unsigned NumPhysRegs;
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/// Tracking - True if RegScavenger is currently tracking the liveness of
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/// registers.
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bool Tracking;
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/// Information on scavenged registers (held in a spill slot).
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struct ScavengedInfo {
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ScavengedInfo(int FI = -1) : FrameIndex(FI), Reg(0), Restore(NULL) {}
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/// A spill slot used for scavenging a register post register allocation.
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int FrameIndex;
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/// If non-zero, the specific register is currently being
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/// scavenged. That is, it is spilled to this scavenging stack slot.
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unsigned Reg;
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/// The instruction that restores the scavenged register from stack.
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const MachineInstr *Restore;
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};
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/// A vector of information on scavenged registers.
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SmallVector<ScavengedInfo, 2> Scavenged;
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/// CalleeSavedrRegs - A bitvector of callee saved registers for the target.
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///
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BitVector CalleeSavedRegs;
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/// RegsAvailable - The current state of all the physical registers immediately
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/// before MBBI. One bit per physical register. If bit is set that means it's
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/// available, unset means the register is currently being used.
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BitVector RegsAvailable;
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// These BitVectors are only used internally to forward(). They are members
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// to avoid frequent reallocations.
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BitVector KillRegs, DefRegs;
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public:
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RegScavenger()
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: MBB(NULL), NumPhysRegs(0), Tracking(false) {}
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/// enterBasicBlock - Start tracking liveness from the begin of the specific
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/// basic block.
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void enterBasicBlock(MachineBasicBlock *mbb);
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/// initRegState - allow resetting register state info for multiple
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/// passes over/within the same function.
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void initRegState();
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/// forward - Move the internal MBB iterator and update register states.
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void forward();
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/// forward - Move the internal MBB iterator and update register states until
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/// it has processed the specific iterator.
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void forward(MachineBasicBlock::iterator I) {
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if (!Tracking && MBB->begin() != I) forward();
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while (MBBI != I) forward();
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}
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/// Invert the behavior of forward() on the current instruction (undo the
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/// changes to the available registers made by forward()).
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void unprocess();
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/// Unprocess instructions until you reach the provided iterator.
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void unprocess(MachineBasicBlock::iterator I) {
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while (MBBI != I) unprocess();
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}
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/// skipTo - Move the internal MBB iterator but do not update register states.
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void skipTo(MachineBasicBlock::iterator I) {
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if (I == MachineBasicBlock::iterator(NULL))
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Tracking = false;
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MBBI = I;
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}
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MachineBasicBlock::iterator getCurrentPosition() const {
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return MBBI;
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}
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/// getRegsUsed - return all registers currently in use in used.
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void getRegsUsed(BitVector &used, bool includeReserved);
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/// getRegsAvailable - Return all available registers in the register class
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/// in Mask.
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BitVector getRegsAvailable(const TargetRegisterClass *RC);
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/// FindUnusedReg - Find a unused register of the specified register class.
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/// Return 0 if none is found.
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unsigned FindUnusedReg(const TargetRegisterClass *RegClass) const;
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/// Add a scavenging frame index.
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void addScavengingFrameIndex(int FI) {
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Scavenged.push_back(ScavengedInfo(FI));
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}
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/// Query whether a frame index is a scavenging frame index.
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bool isScavengingFrameIndex(int FI) const {
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for (SmallVector<ScavengedInfo, 2>::const_iterator I = Scavenged.begin(),
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IE = Scavenged.end(); I != IE; ++I)
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if (I->FrameIndex == FI)
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return true;
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return false;
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}
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/// Get an array of scavenging frame indices.
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void getScavengingFrameIndices(SmallVectorImpl<int> &A) const {
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for (SmallVector<ScavengedInfo, 2>::const_iterator I = Scavenged.begin(),
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IE = Scavenged.end(); I != IE; ++I)
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if (I->FrameIndex >= 0)
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A.push_back(I->FrameIndex);
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}
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/// scavengeRegister - Make a register of the specific register class
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/// available and do the appropriate bookkeeping. SPAdj is the stack
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/// adjustment due to call frame, it's passed along to eliminateFrameIndex().
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/// Returns the scavenged register.
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unsigned scavengeRegister(const TargetRegisterClass *RegClass,
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MachineBasicBlock::iterator I, int SPAdj);
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unsigned scavengeRegister(const TargetRegisterClass *RegClass, int SPAdj) {
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return scavengeRegister(RegClass, MBBI, SPAdj);
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}
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/// setUsed - Tell the scavenger a register is used.
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///
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void setUsed(unsigned Reg);
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private:
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/// isReserved - Returns true if a register is reserved. It is never "unused".
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bool isReserved(unsigned Reg) const { return MRI->isReserved(Reg); }
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/// isUsed - Test if a register is currently being used. When called by the
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/// isAliasUsed function, we only check isReserved if this is the original
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/// register, not an alias register.
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///
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bool isUsed(unsigned Reg, bool CheckReserved = true) const {
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return !RegsAvailable.test(Reg) || (CheckReserved && isReserved(Reg));
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}
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/// isAliasUsed - Is Reg or an alias currently in use?
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bool isAliasUsed(unsigned Reg) const;
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/// setUsed / setUnused - Mark the state of one or a number of registers.
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///
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void setUsed(BitVector &Regs) {
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RegsAvailable.reset(Regs);
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}
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void setUnused(BitVector &Regs) {
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RegsAvailable |= Regs;
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}
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/// Processes the current instruction and fill the KillRegs and DefRegs bit
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/// vectors.
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void determineKillsAndDefs();
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/// Add Reg and all its sub-registers to BV.
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void addRegWithSubRegs(BitVector &BV, unsigned Reg);
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/// findSurvivorReg - Return the candidate register that is unused for the
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/// longest after StartMI. UseMI is set to the instruction where the search
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/// stopped.
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///
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/// No more than InstrLimit instructions are inspected.
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unsigned findSurvivorReg(MachineBasicBlock::iterator StartMI,
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BitVector &Candidates,
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unsigned InstrLimit,
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MachineBasicBlock::iterator &UseMI);
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};
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} // End llvm namespace
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#endif
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