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61396aebee
Most of these tests require a single mov instruction that can come either before or after a 2-addr instruction. -join-physregs changes the behavior, but the results are equivalent. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130891 91177308-0d34-0410-b5e6-96231b3b80d8
50 lines
1.2 KiB
LLVM
50 lines
1.2 KiB
LLVM
; RUN: llc < %s | FileCheck %s
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target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128"
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target triple = "x86_64-apple-darwin8"
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; This should be a single mov, not a load of immediate + andq.
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; CHECK: test:
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; CHECK: movl %edi, %eax
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define i64 @test(i64 %x) nounwind {
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entry:
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%tmp123 = and i64 %x, 4294967295 ; <i64> [#uses=1]
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ret i64 %tmp123
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}
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; This copy can't be coalesced away because it needs the implicit zero-extend.
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; CHECK: bbb:
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; CHECK: movl %edi, %edi
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define void @bbb(i64 %x) nounwind {
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%t = and i64 %x, 4294967295
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call void @foo(i64 %t)
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ret void
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}
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; This should use a 32-bit and with implicit zero-extension, not a 64-bit and
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; with a separate mov to materialize the mask.
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; rdar://7527390
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; CHECK: ccc:
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; CHECK: andl $-1048593, %edi
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declare void @foo(i64 %x) nounwind
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define void @ccc(i64 %x) nounwind {
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%t = and i64 %x, 4293918703
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call void @foo(i64 %t)
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ret void
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}
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; This requires a mov and a 64-bit and.
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; CHECK: ddd:
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; CHECK: movabsq $4294967296, %r
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; CHECK: andq %rax, %rdi
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define void @ddd(i64 %x) nounwind {
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%t = and i64 %x, 4294967296
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call void @foo(i64 %t)
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ret void
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}
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