Weiming Zhao e56764bad1 Remove hard coded registers in ARM ldrexd and strexd instructions ... This patch replaces the hard coded GPR pair [R0, R1] of Intrinsic:arm_ldrexd and [R2, R3] of Intrinsic:arm_strexd with even/odd GPRPair reg class. Similar to the lowering of atomic_64 operation. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@168207 91177308-0d34-0410-b5e6-96231b3b80d8		2012-11-16 21:55:34 +00:00
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AsmMatcherEmitter.cpp
AsmWriterEmitter.cpp
AsmWriterInst.cpp
AsmWriterInst.h
CallingConvEmitter.cpp
CMakeLists.txt
CodeEmitterGen.cpp
CodeGenDAGPatterns.cpp
CodeGenDAGPatterns.h
CodeGenInstruction.cpp
CodeGenInstruction.h
CodeGenIntrinsics.h
CodeGenMapTable.cpp
CodeGenRegisters.cpp
CodeGenRegisters.h
CodeGenSchedule.cpp
CodeGenSchedule.h
CodeGenTarget.cpp
CodeGenTarget.h
DAGISelEmitter.cpp
DAGISelMatcher.cpp
DAGISelMatcher.h
DAGISelMatcherEmitter.cpp
DAGISelMatcherGen.cpp
DAGISelMatcherOpt.cpp
DFAPacketizerEmitter.cpp
DisassemblerEmitter.cpp
EDEmitter.cpp	Remove hard coded registers in ARM ldrexd and strexd instructions	2012-11-16 21:55:34 +00:00
FastISelEmitter.cpp
FixedLenDecoderEmitter.cpp
InstrInfoEmitter.cpp
IntrinsicEmitter.cpp
LLVMBuild.txt
Makefile
PseudoLoweringEmitter.cpp
RegisterInfoEmitter.cpp
SequenceToOffsetTable.h
SetTheory.cpp
SetTheory.h
StringToOffsetTable.h
SubtargetEmitter.cpp
TableGen.cpp
TableGenBackends.h
TGValueTypes.cpp
X86DisassemblerShared.h
X86DisassemblerTables.cpp
X86DisassemblerTables.h
X86ModRMFilters.cpp
X86ModRMFilters.h
X86RecognizableInstr.cpp
X86RecognizableInstr.h