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5f22dd7858
As requested by AArch64 subtargets. Note that this will have no effect until the AArch64 target actually enables the pass like this: substitutePass(&PostRASchedulerID, &PostMachineSchedulerID); As soon as armv7 switches over, PostMachineScheduler will become the default postRA scheduler, so this won't be necessary any more. Targets using the old postRA schedule would then do: substitutePass(&PostMachineSchedulerID, &PostRASchedulerID); git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210167 91177308-0d34-0410-b5e6-96231b3b80d8
62 lines
2.1 KiB
C++
62 lines
2.1 KiB
C++
//===-- TargetSubtargetInfo.cpp - General Target Information ---------------==//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file describes the general parts of a Subtarget.
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//
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//===----------------------------------------------------------------------===//
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#include "llvm/Support/CommandLine.h"
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#include "llvm/ADT/SmallVector.h"
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#include "llvm/Target/TargetSubtargetInfo.h"
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using namespace llvm;
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//---------------------------------------------------------------------------
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// TargetSubtargetInfo Class
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//
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TargetSubtargetInfo::TargetSubtargetInfo() {}
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TargetSubtargetInfo::~TargetSubtargetInfo() {}
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// Temporary option to compare overall performance change when moving from the
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// SD scheduler to the MachineScheduler pass pipeline. This is convenient for
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// benchmarking during the transition from SD to MI scheduling. Once armv7 makes
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// the switch, it should go away. The normal way to enable/disable the
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// MachineScheduling pass itself is by using -enable-misched. For targets that
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// already use MI sched (via MySubTarget::enableMachineScheduler())
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// -misched-bench=false negates the subtarget hook.
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static cl::opt<bool> BenchMachineSched("misched-bench", cl::Hidden,
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cl::desc("Migrate from the target's default SD scheduler to MI scheduler"));
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bool TargetSubtargetInfo::useMachineScheduler() const {
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if (BenchMachineSched.getNumOccurrences())
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return BenchMachineSched;
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return enableMachineScheduler();
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}
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bool TargetSubtargetInfo::enableMachineScheduler() const {
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return false;
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}
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bool TargetSubtargetInfo::enablePostMachineScheduler() const {
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return false;
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}
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bool TargetSubtargetInfo::enablePostRAScheduler(
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CodeGenOpt::Level OptLevel,
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AntiDepBreakMode& Mode,
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RegClassVector& CriticalPathRCs) const {
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Mode = ANTIDEP_NONE;
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CriticalPathRCs.clear();
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return false;
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}
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bool TargetSubtargetInfo::useAA() const {
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return false;
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}
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