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LLVM backend for 6502
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7e56831a68
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Jakob Stoklund Olesen 7e56831a68 Synthesize missing register class intersections. 
The function TRI::getCommonSubClass(A, B) returns the largest common
sub-class of the register classes A and B.  This patch teaches TableGen
to synthesize sub-classes such that the answer is always maximal.

In other words, every register that is in both A and B will also be
present in getCommonSubClass(A, B).

This introduces these synthetic register classes:

ARM:
    GPRnopc_and_hGPR
    GPRnopc_and_hGPR
    hGPR_and_rGPR
    GPRnopc_and_hGPR
    GPRnopc_and_hGPR
    hGPR_and_rGPR
    tGPR_and_tcGPR
    hGPR_and_tcGPR

X86:
    GR32_NOAX_and_GR32_NOSP
    GR32_NOAX_and_GR32_NOREX
    GR64_NOSP_and_GR64_TC
    GR64_NOSP_and_GR64_TC
    GR64_NOREX_and_GR64_TC
    GR32_NOAX_and_GR32_NOSP
    GR32_NOAX_and_GR32_NOREX
    GR32_NOAX_and_GR32_NOREX_NOSP
    GR64_NOSP_and_GR64_TC
    GR64_NOREX_and_GR64_TC
    GR64_NOREX_NOSP_and_GR64_TC
    GR32_NOAX_and_GR32_NOSP
    GR32_NOAX_and_GR32_NOREX
    GR32_NOAX_and_GR32_NOREX_NOSP
    GR32_ABCD_and_GR32_NOAX
    GR32_NOAX_and_GR32_NOSP
    GR32_NOAX_and_GR32_NOREX
    GR32_NOAX_and_GR32_NOREX_NOSP
    GR32_ABCD_and_GR32_NOAX
    GR32_NOAX_and_GR32_TC
    GR32_NOAX_and_GR32_NOSP
    GR64_NOSP_and_GR64_TC
    GR32_NOAX_and_GR32_NOREX
    GR32_NOAX_and_GR32_NOREX_NOSP
    GR64_NOREX_and_GR64_TC
    GR64_NOREX_NOSP_and_GR64_TC
    GR32_ABCD_and_GR32_NOAX
    GR64_ABCD_and_GR64_TC
    GR32_NOAX_and_GR32_TC
    GR32_AD_and_GR32_NOAX

Other targets are unaffected.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146657 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-15 16:48:55 +00:00
autoconf Hexagon backend support 2011-12-12 21:14:40 +00:00
bindings LLVMBuild: Remove trailing newline, which irked me. 2011-12-12 19:48:00 +00:00
cmake cmake: work with CMake < 2.8.5 2011-12-12 13:06:25 +00:00
docs Add a blurb about MachineInstr bundling support. 2011-12-14 22:57:45 +00:00
examples LLVMBuild: Remove trailing newline, which irked me. 2011-12-12 19:48:00 +00:00
include Move Instruction::isSafeToSpeculativelyExecute out of VMCore and 2011-12-14 23:49:11 +00:00
lib Pass optLevel to XCoreDAGToDAGISel. 2011-12-15 15:18:35 +00:00
projects Hexagon backend support 2011-12-12 21:14:40 +00:00
runtime LLVMBuild: Remove trailing newline, which irked me. 2011-12-12 19:48:00 +00:00
test Fix test. 2011-12-15 04:52:47 +00:00
tools llvm-nm: refactor in order to support reading files from stdin. 2011-12-13 23:17:29 +00:00
unittests Revert r146363 to allow buildbots to make forward progress. 2011-12-12 17:58:31 +00:00
utils Synthesize missing register class intersections. 2011-12-15 16:48:55 +00:00
.gitignore git: Add tools/lldb to the ignore list. 2011-11-10 22:55:50 +00:00
CMakeLists.txt Don't default the *cached* list of targets to build to an explicit list 2011-12-13 02:19:11 +00:00
configure Hexagon backend support 2011-12-12 21:14:40 +00:00
CREDITS.TXT CREDITS.TXT: Add a line. (test commit) 2011-10-29 23:42:14 +00:00
LICENSE.TXT
llvm.spec.in
LLVMBuild.txt LLVMBuild: Introduce a common section which currently has a list of the 2011-12-12 22:45:54 +00:00
Makefile llvm-config: Replace with C++ version (was llvm-config-2). 2011-12-01 20:18:09 +00:00
Makefile.common
Makefile.config.in Add an optional separate install prefix for internal components. rdar://10217046 2011-11-28 07:59:52 +00:00
Makefile.rules Add a deterministic finite automaton based packetizer for VLIW architectures 2011-12-01 21:10:21 +00:00
README.txt Undo test commit 2011-11-22 20:05:48 +00:00

README.txt 

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