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Changing 'op' here caused us to not enter the store into a map, causing reemission of the code!! In practice, a simple loop like this: no_exit: ; preds = %no_exit, %entry %indvar = phi uint [ %indvar.next, %no_exit ], [ 0, %entry ] ; <uint> [#uses=3] %tmp.4 = getelementptr "complex long double"* %P, uint %indvar, uint 0 ; <double*> [#uses=1] store double 0.000000e+00, double* %tmp.4 %indvar.next = add uint %indvar, 1 ; <uint> [#uses=2] %exitcond = seteq uint %indvar.next, %N ; <bool> [#uses=1] br bool %exitcond, label %return, label %no_exit was being code gen'd to: .LBBtest_1: # no_exit movl %edx, %esi shll $4, %esi movl $0, 4(%eax,%esi) movl $0, (%eax,%esi) incl %edx movl $0, (%eax,%esi) movl $0, 4(%eax,%esi) cmpl %ecx, %edx jne .LBBtest_1 # no_exit Note that we are doing 4 32-bit stores instead of 2. Now we generate: .LBBtest_1: # no_exit movl %edx, %esi incl %esi shll $4, %edx movl $0, (%eax,%edx) movl $0, 4(%eax,%edx) cmpl %ecx, %esi movl %esi, %edx jne .LBBtest_1 # no_exit This is much happier, though it would be even better if the increment of ESI was scheduled after the compare :-/ git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@20265 91177308-0d34-0410-b5e6-96231b3b80d8 |
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.. | ||
SelectionDAG | ||
AsmPrinter.cpp | ||
BranchFolding.cpp | ||
IntrinsicLowering.cpp | ||
LiveInterval.cpp | ||
LiveInterval.h | ||
LiveIntervalAnalysis.cpp | ||
LiveIntervalAnalysis.h | ||
LiveVariables.cpp | ||
MachineBasicBlock.cpp | ||
MachineCodeEmitter.cpp | ||
MachineFunction.cpp | ||
MachineInstr.cpp | ||
Makefile | ||
Passes.cpp | ||
PHIElimination.cpp | ||
PhysRegTracker.h | ||
PrologEpilogInserter.cpp | ||
RegAllocIterativeScan.cpp | ||
RegAllocLinearScan.cpp | ||
RegAllocLocal.cpp | ||
RegAllocSimple.cpp | ||
TwoAddressInstructionPass.cpp | ||
UnreachableBlockElim.cpp | ||
VirtRegMap.cpp | ||
VirtRegMap.h |