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LLVM backend for 6502
7ea151449d
I suggested this change in D7898 (http://llvm.org/viewvc/llvm-project?view=revision&revision=231354) It improves the v4i64 case although not optimally. This AVX codegen: vmovq {{.*#+}} xmm0 = mem[0],zero vxorpd %ymm1, %ymm1, %ymm1 vblendpd {{.*#+}} ymm0 = ymm0[0],ymm1[1,2,3] Becomes: vmovsd {{.*#+}} xmm0 = mem[0],zero Unfortunately, this doesn't completely solve PR22685. There are still at least 2 problems under here: We're not handling v32i8 / v16i16. We're not getting the FP / int domains right for instruction selection. But since this patch alone appears to do no harm, reduces code duplication, and helps v4i64, I'm submitting this patch ahead of fixing the above. Differential Revision: http://reviews.llvm.org/D8341 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@233704 91177308-0d34-0410-b5e6-96231b3b80d8 |
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test | ||
tools | ||
unittests | ||
utils | ||
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.gitignore | ||
CMakeLists.txt | ||
CODE_OWNERS.TXT | ||
configure | ||
CREDITS.TXT | ||
LICENSE.TXT | ||
llvm.spec.in | ||
LLVMBuild.txt | ||
Makefile | ||
Makefile.common | ||
Makefile.config.in | ||
Makefile.rules | ||
README.txt |
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