mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-11-06 21:05:51 +00:00
7eacad03ef
Vectors were being manually scalarized by the backend. Instead, let the target-independent code do all of the work. The manual scalarization was from a time before good target-independent support for scalarization in LLVM. However, this forces us to specially-handle vector loads and stores, which we can turn into PTX instructions that produce/consume multiple operands. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174968 91177308-0d34-0410-b5e6-96231b3b80d8
65 lines
2.7 KiB
TableGen
65 lines
2.7 KiB
TableGen
//===-- NVPTXRegisterInfo.td - NVPTX Register defs ---------*- tablegen -*-===//
|
|
//
|
|
// The LLVM Compiler Infrastructure
|
|
//
|
|
// This file is distributed under the University of Illinois Open Source
|
|
// License. See LICENSE.TXT for details.
|
|
//
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// Declarations that describe the PTX register file
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
class NVPTXReg<string n> : Register<n> {
|
|
let Namespace = "NVPTX";
|
|
}
|
|
|
|
class NVPTXRegClass<list<ValueType> regTypes, int alignment, dag regList>
|
|
: RegisterClass <"NVPTX", regTypes, alignment, regList>;
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// Registers
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
// Special Registers used as stack pointer
|
|
def VRFrame : NVPTXReg<"%SP">;
|
|
def VRFrameLocal : NVPTXReg<"%SPL">;
|
|
|
|
// Special Registers used as the stack
|
|
def VRDepot : NVPTXReg<"%Depot">;
|
|
|
|
foreach i = 0-395 in {
|
|
def P#i : NVPTXReg<"%p"#i>; // Predicate
|
|
def RC#i : NVPTXReg<"%rc"#i>; // 8-bit
|
|
def RS#i : NVPTXReg<"%rs"#i>; // 16-bit
|
|
def R#i : NVPTXReg<"%r"#i>; // 32-bit
|
|
def RL#i : NVPTXReg<"%rl"#i>; // 64-bit
|
|
def F#i : NVPTXReg<"%f"#i>; // 32-bit float
|
|
def FL#i : NVPTXReg<"%fl"#i>; // 64-bit float
|
|
|
|
// Arguments
|
|
def ia#i : NVPTXReg<"%ia"#i>;
|
|
def la#i : NVPTXReg<"%la"#i>;
|
|
def fa#i : NVPTXReg<"%fa"#i>;
|
|
def da#i : NVPTXReg<"%da"#i>;
|
|
}
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// Register classes
|
|
//===----------------------------------------------------------------------===//
|
|
def Int1Regs : NVPTXRegClass<[i1], 8, (add (sequence "P%u", 0, 395))>;
|
|
def Int8Regs : NVPTXRegClass<[i8], 8, (add (sequence "RC%u", 0, 395))>;
|
|
def Int16Regs : NVPTXRegClass<[i16], 16, (add (sequence "RS%u", 0, 395))>;
|
|
def Int32Regs : NVPTXRegClass<[i32], 32, (add (sequence "R%u", 0, 395))>;
|
|
def Int64Regs : NVPTXRegClass<[i64], 64, (add (sequence "RL%u", 0, 395))>;
|
|
def Float32Regs : NVPTXRegClass<[f32], 32, (add (sequence "F%u", 0, 395))>;
|
|
def Float64Regs : NVPTXRegClass<[f64], 64, (add (sequence "FL%u", 0, 395))>;
|
|
def Int32ArgRegs : NVPTXRegClass<[i32], 32, (add (sequence "ia%u", 0, 395))>;
|
|
def Int64ArgRegs : NVPTXRegClass<[i64], 64, (add (sequence "la%u", 0, 395))>;
|
|
def Float32ArgRegs : NVPTXRegClass<[f32], 32, (add (sequence "fa%u", 0, 395))>;
|
|
def Float64ArgRegs : NVPTXRegClass<[f64], 64, (add (sequence "da%u", 0, 395))>;
|
|
|
|
// Read NVPTXRegisterInfo.cpp to see how VRFrame and VRDepot are used.
|
|
def SpecialRegs : NVPTXRegClass<[i32], 32, (add VRFrame, VRDepot)>;
|