llvm-6502/test/CodeGen/CellSPU
Cameron Zwarich 899eaa3569 Roll r127459 back in:
Optimize trivial branches in CodeGenPrepare, which often get created from the
lowering of objectsize intrinsics. Unfortunately, a number of tests were relying
on llc not optimizing trivial branches, so I had to add an option to allow them
to continue to test what they originally tested.

This fixes <rdar://problem/8785296> and <rdar://problem/9112893>.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127498 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-11 21:52:04 +00:00
..
useful-harnesses
2009-01-01-BrCond.ll
2010-04-07-DbgValueOtherTargets.ll
and_ops.ll
arg_ret.ll
bigstack.ll
bss.ll Be nice to Xcore and the XMOS assembler and avoid quoting section names 2011-03-04 20:03:14 +00:00
call_indirect.ll
call.ll
crash.ll
ctpop.ll
dg.exp
div_ops.ll
dp_farith.ll
eqv.ll
extract_elt.ll
fcmp32.ll
fcmp64.ll
fdiv.ll
fneg-fabs.ll
i8ops.ll
i64ops.ll
icmp8.ll
icmp16.ll
icmp32.ll
icmp64.ll
immed16.ll
immed32.ll
immed64.ll
int2fp.ll
intrinsics_branch.ll
intrinsics_float.ll
intrinsics_logical.ll
jumptable.ll Roll r127459 back in: 2011-03-11 21:52:04 +00:00
loads.ll Allow load from constant on SPU. 2011-03-04 12:00:11 +00:00
mul_ops.ll
mul-with-overflow.ll
nand.ll
or_ops.ll
private.ll
rotate_ops.ll Fix mistyped CHECK lines. 2011-03-09 22:07:31 +00:00
select_bits.ll
sext128.ll
shift_ops.ll Allow vector shifts (shl,lshr,ashr) on SPU. 2011-03-04 13:19:18 +00:00
shuffles.ll
sp_farith.ll
stores.ll Allow load from constant on SPU. 2011-03-04 12:00:11 +00:00
storestruct.ll
struct_1.ll
sub_ops.ll
trunc.ll
v2f32.ll
v2i32.ll
vec_const.ll
vecinsert.ll