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llvm-6502/test/CodeGen/Mips/buildpairextractelementf64.ll
Akira Hatanaka b1f4f120a5 [mips] Add support for mfhc1 and mthc1.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188848 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-20 23:47:25 +00:00

35 lines
764 B
LLVM

; RUN: llc -march=mipsel < %s | FileCheck %s -check-prefix=FP32
; RUN: llc -march=mips < %s | FileCheck %s -check-prefix=FP32
; RUN: llc -march=mipsel -mattr=+fp64 < %s | FileCheck %s -check-prefix=FP64
; RUN: llc -march=mips -mattr=+fp64 < %s | FileCheck %s -check-prefix=FP64
@a = external global i32
; CHECK-LABEL: f:
; FP32: mtc1
; FP32: mtc1
; FP64-DAG: mtc1
; FP64-DAG: mthc1
define double @f(i32 %a1, double %d) nounwind {
entry:
store i32 %a1, i32* @a, align 4
%add = fadd double %d, 2.000000e+00
ret double %add
}
; CHECK-LABEL: f3:
; FP32: mfc1
; FP32: mfc1
; FP64-DAG: mfc1
; FP64-DAG: mfhc1
define void @f3(double %d, i32 %a1) nounwind {
entry:
tail call void @f2(i32 %a1, double %d) nounwind
ret void
}
declare void @f2(i32, double)