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https://github.com/c64scene-ar/llvm-6502.git
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e2d6f91d63
For some reason I never got around to adding these at the same time as the signed versions. No idea why. I'm not sure whether this SystemZII::BranchC* stuff is useful, or whether it should just be replaced with an "is normal" flag. I'll leave that for later though. There are some boundary conditions that can be tweaked, such as preferring unsigned comparisons for equality with [128, 256), and "<= 255" over "< 256", but again I'll leave those for a separate patch. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190930 91177308-0d34-0410-b5e6-96231b3b80d8
108 lines
3.4 KiB
Python
108 lines
3.4 KiB
Python
# Test 32-bit COMPARE LOGICAL AND BRANCH in cases where the sheer number of
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# instructions causes some branches to be out of range.
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# RUN: python %s | llc -mtriple=s390x-linux-gnu | FileCheck %s
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# Construct:
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#
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# before0:
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# conditional branch to after0
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# ...
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# beforeN:
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# conditional branch to after0
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# main:
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# 0xffcc bytes, from MVIY instructions
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# conditional branch to main
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# after0:
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# ...
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# conditional branch to main
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# afterN:
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#
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# Each conditional branch sequence occupies 12 bytes if it uses a short
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# branch and 14 if it uses a long one. The ones before "main:" have to
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# take the branch length into account, which is 6 for short branches,
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# so the final (0x34 - 6) / 12 == 3 blocks can use short branches.
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# The ones after "main:" do not, so the first 0x34 / 12 == 4 blocks
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# can use short branches.
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#
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# CHECK: lb [[REG:%r[0-5]]], 0(%r3)
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# CHECK: clr %r4, [[REG]]
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# CHECK: jgl [[LABEL:\.L[^ ]*]]
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# CHECK: lb [[REG:%r[0-5]]], 1(%r3)
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# CHECK: clr %r4, [[REG]]
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# CHECK: jgl [[LABEL]]
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# CHECK: lb [[REG:%r[0-5]]], 2(%r3)
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# CHECK: clr %r4, [[REG]]
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# CHECK: jgl [[LABEL]]
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# CHECK: lb [[REG:%r[0-5]]], 3(%r3)
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# CHECK: clr %r4, [[REG]]
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# CHECK: jgl [[LABEL]]
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# CHECK: lb [[REG:%r[0-5]]], 4(%r3)
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# CHECK: clr %r4, [[REG]]
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# CHECK: jgl [[LABEL]]
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# CHECK: lb [[REG:%r[0-5]]], 5(%r3)
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# CHECK: clrjl %r4, [[REG]], [[LABEL]]
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# CHECK: lb [[REG:%r[0-5]]], 6(%r3)
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# CHECK: clrjl %r4, [[REG]], [[LABEL]]
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# CHECK: lb [[REG:%r[0-5]]], 7(%r3)
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# CHECK: clrjl %r4, [[REG]], [[LABEL]]
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# ...main goes here...
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# CHECK: lb [[REG:%r[0-5]]], 25(%r3)
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# CHECK: clrjl %r4, [[REG]], [[LABEL:\.L[^ ]*]]
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# CHECK: lb [[REG:%r[0-5]]], 26(%r3)
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# CHECK: clrjl %r4, [[REG]], [[LABEL]]
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# CHECK: lb [[REG:%r[0-5]]], 27(%r3)
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# CHECK: clrjl %r4, [[REG]], [[LABEL]]
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# CHECK: lb [[REG:%r[0-5]]], 28(%r3)
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# CHECK: clrjl %r4, [[REG]], [[LABEL]]
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# CHECK: lb [[REG:%r[0-5]]], 29(%r3)
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# CHECK: clr %r4, [[REG]]
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# CHECK: jgl [[LABEL]]
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# CHECK: lb [[REG:%r[0-5]]], 30(%r3)
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# CHECK: clr %r4, [[REG]]
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# CHECK: jgl [[LABEL]]
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# CHECK: lb [[REG:%r[0-5]]], 31(%r3)
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# CHECK: clr %r4, [[REG]]
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# CHECK: jgl [[LABEL]]
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# CHECK: lb [[REG:%r[0-5]]], 32(%r3)
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# CHECK: clr %r4, [[REG]]
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# CHECK: jgl [[LABEL]]
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branch_blocks = 8
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main_size = 0xffcc
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print 'define void @f1(i8 *%base, i8 *%stop, i32 %limit) {'
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print 'entry:'
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print ' br label %before0'
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print ''
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for i in xrange(branch_blocks):
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next = 'before%d' % (i + 1) if i + 1 < branch_blocks else 'main'
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print 'before%d:' % i
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print ' %%bstop%d = getelementptr i8 *%%stop, i64 %d' % (i, i)
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print ' %%bcur%d = load volatile i8 *%%bstop%d' % (i, i)
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print ' %%bext%d = sext i8 %%bcur%d to i32' % (i, i)
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print ' %%btest%d = icmp ult i32 %%limit, %%bext%d' % (i, i)
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print ' br i1 %%btest%d, label %%after0, label %%%s' % (i, next)
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print ''
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print '%s:' % next
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a, b = 1, 1
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for i in xrange(0, main_size, 6):
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a, b = b, a + b
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offset = 4096 + b % 500000
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value = a % 256
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print ' %%ptr%d = getelementptr i8 *%%base, i64 %d' % (i, offset)
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print ' store volatile i8 %d, i8 *%%ptr%d' % (value, i)
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for i in xrange(branch_blocks):
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print ' %%astop%d = getelementptr i8 *%%stop, i64 %d' % (i, i + 25)
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print ' %%acur%d = load volatile i8 *%%astop%d' % (i, i)
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print ' %%aext%d = sext i8 %%acur%d to i32' % (i, i)
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print ' %%atest%d = icmp ult i32 %%limit, %%aext%d' % (i, i)
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print ' br i1 %%atest%d, label %%main, label %%after%d' % (i, i)
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print ''
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print 'after%d:' % i
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print ' ret void'
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print '}'
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