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https://github.com/c64scene-ar/llvm-6502.git
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5ad021c8d4
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@14874 91177308-0d34-0410-b5e6-96231b3b80d8
59 lines
2.1 KiB
C++
59 lines
2.1 KiB
C++
//===-- SkeletonTargetMachine.cpp - Define TargetMachine for Skeleton -----===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file was developed by the LLVM research group and is distributed under
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// the University of Illinois Open Source License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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//
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//===----------------------------------------------------------------------===//
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#include "SkeletonTargetMachine.h"
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#include "Skeleton.h"
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#include "llvm/Module.h"
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#include "llvm/PassManager.h"
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#include "llvm/Target/TargetOptions.h"
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#include "llvm/Target/TargetMachineRegistry.h"
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/CodeGen/Passes.h"
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using namespace llvm;
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namespace {
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// Register the target.
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RegisterTarget<SkeletonTargetMachine> X("skeleton",
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" Target Skeleton (unusable)");
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}
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/// SkeletonTargetMachine ctor - Create an ILP32 architecture model
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///
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SkeletonTargetMachine::SkeletonTargetMachine(const Module &M,
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IntrinsicLowering *IL)
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: TargetMachine("Skeleton", IL, true, 4, 4, 4, 4, 4),
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FrameInfo(TargetFrameInfo::StackGrowsDown, 8, -4), JITInfo(*this) {
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}
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/// addPassesToEmitAssembly - Add passes to the specified pass manager
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/// to implement a static compiler for this target.
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///
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bool SkeletonTargetMachine::addPassesToEmitAssembly(PassManager &PM,
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std::ostream &Out) {
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// <insert instruction selector passes here>
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PM.add(createRegisterAllocator());
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PM.add(createPrologEpilogCodeInserter());
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// <insert assembly code output passes here>
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PM.add(createMachineCodeDeleter());
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return true; // change to `return false' when this actually works.
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}
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/// addPassesToJITCompile - Add passes to the specified pass manager to
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/// implement a fast dynamic compiler for this target.
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///
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void SkeletonJITInfo::addPassesToJITCompile(FunctionPassManager &PM) {
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// <insert instruction selector passes here>
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PM.add(createRegisterAllocator());
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PM.add(createPrologEpilogCodeInserter());
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}
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