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7f35455708
in-register, such that we can use a single vector store rather then a series of scalar stores. For func_4_8 the generated code vldr d16, LCPI0_0 vmov d17, r0, r1 vadd.i16 d16, d17, d16 vmov.u16 r0, d16[3] strb r0, [r2, #3] vmov.u16 r0, d16[2] strb r0, [r2, #2] vmov.u16 r0, d16[1] strb r0, [r2, #1] vmov.u16 r0, d16[0] strb r0, [r2] bx lr becomes vldr d16, LCPI0_0 vmov d17, r0, r1 vadd.i16 d16, d17, d16 vuzp.8 d16, d17 vst1.32 {d16[0]}, [r2, :32] bx lr I'm not fond of how this combine pessimizes 2012-03-13-DAGCombineBug.ll, but I couldn't think of a way to judiciously apply this combine. This ldrh r0, [r0, #4] strh r0, [r1] becomes vldr d16, [r0] vmov.u16 r0, d16[2] vmov.32 d16[0], r0 vuzp.16 d16, d17 vst1.32 {d16[0]}, [r1, :32] PR11158 rdar://10703339 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154340 91177308-0d34-0410-b5e6-96231b3b80d8
20 lines
524 B
LLVM
20 lines
524 B
LLVM
; RUN: llc -mcpu=cortex-a9 -mtriple=arm-linux-unknown -promote-elements -mattr=+neon < %s | FileCheck %s
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; CHECK: func_4_8
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; CHECK: vst1.32
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; CHECK-NEXT: bx lr
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define void @func_4_8(<4 x i8> %param, <4 x i8>* %p) {
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%r = add <4 x i8> %param, <i8 1, i8 2, i8 3, i8 4>
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store <4 x i8> %r, <4 x i8>* %p
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ret void
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}
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; CHECK: func_2_16
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; CHECK: vst1.32
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; CHECK-NEXT: bx lr
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define void @func_2_16(<2 x i16> %param, <2 x i16>* %p) {
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%r = add <2 x i16> %param, <i16 1, i16 2>
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store <2 x i16> %r, <2 x i16>* %p
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ret void
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}
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