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7fcd5f8c8904ec273bf4baceeb2c12c221934d70
llvm-6502/test/MC/Mips/mips5
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Toma Tabacu e40de571ad [mips] Move 32-bit ADDiu instruction alias from Mips64InstrInfo.td to MipsInstrInfo.td.
Patch by Vasileios Kalintiris.

Differential Revision: http://reviews.llvm.org/D5244



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@217868 91177308-0d34-0410-b5e6-96231b3b80d8
2014-09-16 10:19:03 +00:00
..
invalid-mips32.s
[mips] SYNC $stype instruction was added in Mips32
2014-06-18 17:10:30 +00:00
invalid-mips64.s
[mips] Implement jr.hb and jalr.hb (Jump Register and Jump and Link Register with Hazard Barrier).
2014-06-11 15:05:56 +00:00
invalid-mips64r2-xfail.s
[mips] Test that IAS for -mcpu=mips5 does not accept MIPS64 insns and -mcpu=mips(5|64) does not accept MIPS64r2
2014-05-14 15:35:03 +00:00
invalid-mips64r2.s
[mips] Test that IAS for -mcpu=mips5 does not accept MIPS64 insns and -mcpu=mips(5|64) does not accept MIPS64r2
2014-05-14 15:35:03 +00:00
valid-xfail.s
Revert: r215698 - Current implementation of c.cond.fmt instructions only accept default cc0 register...
2014-08-17 19:47:47 +00:00
valid.s
[mips] Move 32-bit ADDiu instruction alias from Mips64InstrInfo.td to MipsInstrInfo.td.
2014-09-16 10:19:03 +00:00
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