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6520e20e4f
and add a TargetLowering hook for it to use to determine when this is legal (i.e. not in PIC mode, etc.) This allows instruction selection to emit folded constant offsets in more cases, such as the included testcase, eliminating the need for explicit arithmetic instructions. This eliminates the need for the C++ code in X86ISelDAGToDAG.cpp that attempted to achieve the same effect, but wasn't as effective. Also, fix handling of offsets in GlobalAddressSDNodes in several places, including changing GlobalAddressSDNode's offset from int to int64_t. The Mips, Alpha, Sparc, and CellSPU targets appear to be unaware of GlobalAddress offsets currently, so set the hook to false on those targets. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@57748 91177308-0d34-0410-b5e6-96231b3b80d8
19 lines
508 B
LLVM
19 lines
508 B
LLVM
; RUN: llvm-as < %s | llc -march=x86 > %t
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; RUN: not grep lea %t
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; RUN: not grep add %t
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; RUN: grep mov %t | count 1
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; RUN: llvm-as < %s | llc -march=x86-64 -relocation-model=static > %t
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; RUN: not grep lea %t
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; RUN: not grep add %t
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; RUN: grep mov %t | count 1
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; This store should fold to a single mov instruction.
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@ptr = global i32* null
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@dst = global [131072 x i32] zeroinitializer
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define void @foo() nounwind {
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store i32* getelementptr ([131072 x i32]* @dst, i32 0, i32 16), i32** @ptr
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ret void
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}
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