mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2025-02-25 03:30:37 +00:00
b6ea67e027
Simplifying Triple::parseARMArch, leaving all the parsing to ARMTargetParser.
This commit also adds AArch64 detection to ARMTargetParser canonicalization,
and a two RedHat arch names (v{6,7}hl, meaning hard-float / little-endian).
Adding enough unit tests to cover the basics. Clang checks fine.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@237902 91177308-0d34-0410-b5e6-96231b3b80d8
392 lines
14 KiB
C++
392 lines
14 KiB
C++
//===-- TargetParser - Parser for target features ---------------*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file implements a target parser to recognise hardware features such as
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// FPU/CPU/ARCH names as well as specific support such as HDIV, etc.
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//
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//===----------------------------------------------------------------------===//
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#include "llvm/Support/ARMBuildAttributes.h"
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#include "llvm/Support/TargetParser.h"
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#include "llvm/ADT/StringExtras.h"
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#include "llvm/ADT/StringSwitch.h"
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using namespace llvm;
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namespace {
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// List of canonical FPU names (use getFPUSynonym)
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// FIXME: TableGen this.
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struct {
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const char * Name;
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ARM::FPUKind ID;
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} FPUNames[] = {
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{ "invalid", ARM::FK_INVALID },
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{ "vfp", ARM::FK_VFP },
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{ "vfpv2", ARM::FK_VFPV2 },
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{ "vfpv3", ARM::FK_VFPV3 },
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{ "vfpv3-d16", ARM::FK_VFPV3_D16 },
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{ "vfpv4", ARM::FK_VFPV4 },
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{ "vfpv4-d16", ARM::FK_VFPV4_D16 },
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{ "fpv5-d16", ARM::FK_FPV5_D16 },
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{ "fp-armv8", ARM::FK_FP_ARMV8 },
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{ "neon", ARM::FK_NEON },
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{ "neon-vfpv4", ARM::FK_NEON_VFPV4 },
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{ "neon-fp-armv8", ARM::FK_NEON_FP_ARMV8 },
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{ "crypto-neon-fp-armv8", ARM::FK_CRYPTO_NEON_FP_ARMV8 },
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{ "softvfp", ARM::FK_SOFTVFP }
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};
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// List of canonical arch names (use getArchSynonym)
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// FIXME: TableGen this.
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struct {
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const char *Name;
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ARM::ArchKind ID;
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const char *DefaultCPU;
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ARMBuildAttrs::CPUArch DefaultArch;
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} ARCHNames[] = {
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{ "invalid", ARM::AK_INVALID, nullptr, ARMBuildAttrs::CPUArch::Pre_v4 },
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{ "armv2", ARM::AK_ARMV2, "2", ARMBuildAttrs::CPUArch::v4 },
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{ "armv2a", ARM::AK_ARMV2A, "2A", ARMBuildAttrs::CPUArch::v4 },
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{ "armv3", ARM::AK_ARMV3, "3", ARMBuildAttrs::CPUArch::v4 },
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{ "armv3m", ARM::AK_ARMV3M, "3M", ARMBuildAttrs::CPUArch::v4 },
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{ "armv4", ARM::AK_ARMV4, "4", ARMBuildAttrs::CPUArch::v4 },
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{ "armv4t", ARM::AK_ARMV4T, "4T", ARMBuildAttrs::CPUArch::v4T },
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{ "armv5", ARM::AK_ARMV5, "5", ARMBuildAttrs::CPUArch::v5T },
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{ "armv5t", ARM::AK_ARMV5T, "5T", ARMBuildAttrs::CPUArch::v5T },
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{ "armv5te", ARM::AK_ARMV5TE, "5TE", ARMBuildAttrs::CPUArch::v5TE },
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{ "armv6", ARM::AK_ARMV6, "6", ARMBuildAttrs::CPUArch::v6 },
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{ "armv6j", ARM::AK_ARMV6J, "6J", ARMBuildAttrs::CPUArch::v6 },
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{ "armv6k", ARM::AK_ARMV6K, "6K", ARMBuildAttrs::CPUArch::v6K },
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{ "armv6t2", ARM::AK_ARMV6T2, "6T2", ARMBuildAttrs::CPUArch::v6T2 },
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{ "armv6z", ARM::AK_ARMV6Z, "6Z", ARMBuildAttrs::CPUArch::v6KZ },
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{ "armv6zk", ARM::AK_ARMV6ZK, "6ZK", ARMBuildAttrs::CPUArch::v6KZ },
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{ "armv6-m", ARM::AK_ARMV6M, "6-M", ARMBuildAttrs::CPUArch::v6_M },
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{ "armv7", ARM::AK_ARMV7, "7", ARMBuildAttrs::CPUArch::v7 },
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{ "armv7-a", ARM::AK_ARMV7A, "7-A", ARMBuildAttrs::CPUArch::v7 },
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{ "armv7-r", ARM::AK_ARMV7R, "7-R", ARMBuildAttrs::CPUArch::v7 },
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{ "armv7-m", ARM::AK_ARMV7M, "7-M", ARMBuildAttrs::CPUArch::v7 },
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{ "armv8-a", ARM::AK_ARMV8A, "8-A", ARMBuildAttrs::CPUArch::v8 },
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{ "armv8.1-a", ARM::AK_ARMV8_1A, "8.1-A", ARMBuildAttrs::CPUArch::v8 },
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// Non-standard Arch names.
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{ "iwmmxt", ARM::AK_IWMMXT, "iwmmxt", ARMBuildAttrs::CPUArch::v5TE },
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{ "iwmmxt2", ARM::AK_IWMMXT2, "iwmmxt2", ARMBuildAttrs::CPUArch::v5TE },
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{ "xscale", ARM::AK_XSCALE, "xscale", ARMBuildAttrs::CPUArch::v5TE },
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{ "armv5e", ARM::AK_ARMV5E, "5E", ARMBuildAttrs::CPUArch::v5TE },
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{ "armv5tej", ARM::AK_ARMV5TEJ, "5TE", ARMBuildAttrs::CPUArch::v5TE },
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{ "armv6sm", ARM::AK_ARMV6SM, "6-M", ARMBuildAttrs::CPUArch::v6_M },
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{ "armv6hl", ARM::AK_ARMV6HL, "6-M", ARMBuildAttrs::CPUArch::v6_M },
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{ "armv7e-m", ARM::AK_ARMV7EM, "7E-M", ARMBuildAttrs::CPUArch::v7E_M },
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{ "armv7l", ARM::AK_ARMV7L, "7-L", ARMBuildAttrs::CPUArch::v7 },
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{ "armv7hl", ARM::AK_ARMV7HL, "7H-L", ARMBuildAttrs::CPUArch::v7 },
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{ "armv7s", ARM::AK_ARMV7S, "7-S", ARMBuildAttrs::CPUArch::v7 }
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};
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// List of canonical ARCH names (use getARCHSynonym)
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// FIXME: TableGen this.
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struct {
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const char *Name;
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ARM::ArchExtKind ID;
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} ARCHExtNames[] = {
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{ "invalid", ARM::AEK_INVALID },
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{ "crc", ARM::AEK_CRC },
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{ "crypto", ARM::AEK_CRYPTO },
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{ "fp", ARM::AEK_FP },
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{ "idiv", ARM::AEK_HWDIV },
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{ "mp", ARM::AEK_MP },
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{ "sec", ARM::AEK_SEC },
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{ "virt", ARM::AEK_VIRT }
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};
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// List of CPU names and their arches.
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// The same CPU can have multiple arches and can be default on multiple arches.
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// When finding the Arch for a CPU, first-found prevails. Sort them accordingly.
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// FIXME: TableGen this.
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struct {
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const char *Name;
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ARM::ArchKind ArchID;
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bool Default;
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} CPUNames[] = {
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{ "arm2", ARM::AK_ARMV2, true },
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{ "arm6", ARM::AK_ARMV3, true },
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{ "arm7m", ARM::AK_ARMV3M, true },
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{ "strongarm", ARM::AK_ARMV4, true },
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{ "arm7tdmi", ARM::AK_ARMV4T, true },
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{ "arm7tdmi-s", ARM::AK_ARMV4T, false },
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{ "arm710t", ARM::AK_ARMV4T, false },
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{ "arm720t", ARM::AK_ARMV4T, false },
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{ "arm9", ARM::AK_ARMV4T, false },
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{ "arm9tdmi", ARM::AK_ARMV4T, false },
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{ "arm920", ARM::AK_ARMV4T, false },
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{ "arm920t", ARM::AK_ARMV4T, false },
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{ "arm922t", ARM::AK_ARMV4T, false },
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{ "arm9312", ARM::AK_ARMV4T, false },
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{ "arm940t", ARM::AK_ARMV4T, false },
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{ "ep9312", ARM::AK_ARMV4T, false },
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{ "arm10tdmi", ARM::AK_ARMV5, true },
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{ "arm10tdmi", ARM::AK_ARMV5T, true },
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{ "arm1020t", ARM::AK_ARMV5T, false },
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{ "xscale", ARM::AK_XSCALE, true },
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{ "xscale", ARM::AK_ARMV5TE, false },
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{ "arm9e", ARM::AK_ARMV5TE, false },
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{ "arm926ej-s", ARM::AK_ARMV5TE, false },
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{ "arm946ej-s", ARM::AK_ARMV5TE, false },
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{ "arm966e-s", ARM::AK_ARMV5TE, false },
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{ "arm968e-s", ARM::AK_ARMV5TE, false },
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{ "arm1020e", ARM::AK_ARMV5TE, false },
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{ "arm1022e", ARM::AK_ARMV5TE, true },
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{ "iwmmxt", ARM::AK_ARMV5TE, false },
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{ "iwmmxt", ARM::AK_IWMMXT, true },
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{ "arm1136jf-s", ARM::AK_ARMV6, true },
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{ "arm1136j-s", ARM::AK_ARMV6J, true },
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{ "arm1136jz-s", ARM::AK_ARMV6J, false },
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{ "arm1176j-s", ARM::AK_ARMV6K, false },
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{ "mpcore", ARM::AK_ARMV6K, false },
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{ "mpcorenovfp", ARM::AK_ARMV6K, false },
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{ "arm1176jzf-s", ARM::AK_ARMV6K, true },
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{ "arm1176jzf-s", ARM::AK_ARMV6Z, true },
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{ "arm1176jzf-s", ARM::AK_ARMV6ZK, true },
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{ "arm1156t2-s", ARM::AK_ARMV6T2, true },
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{ "arm1156t2f-s", ARM::AK_ARMV6T2, false },
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{ "cortex-m0", ARM::AK_ARMV6M, true },
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{ "cortex-m0plus", ARM::AK_ARMV6M, false },
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{ "cortex-m1", ARM::AK_ARMV6M, false },
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{ "sc000", ARM::AK_ARMV6M, false },
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{ "cortex-a8", ARM::AK_ARMV7, true },
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{ "cortex-a5", ARM::AK_ARMV7A, false },
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{ "cortex-a7", ARM::AK_ARMV7A, false },
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{ "cortex-a8", ARM::AK_ARMV7A, true },
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{ "cortex-a9", ARM::AK_ARMV7A, false },
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{ "cortex-a12", ARM::AK_ARMV7A, false },
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{ "cortex-a15", ARM::AK_ARMV7A, false },
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{ "cortex-a17", ARM::AK_ARMV7A, false },
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{ "krait", ARM::AK_ARMV7A, false },
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{ "cortex-r4", ARM::AK_ARMV7R, true },
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{ "cortex-r4f", ARM::AK_ARMV7R, false },
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{ "cortex-r5", ARM::AK_ARMV7R, false },
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{ "cortex-r7", ARM::AK_ARMV7R, false },
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{ "sc300", ARM::AK_ARMV7M, false },
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{ "cortex-m3", ARM::AK_ARMV7M, true },
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{ "cortex-m4", ARM::AK_ARMV7M, false },
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{ "cortex-m7", ARM::AK_ARMV7M, false },
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{ "cortex-a53", ARM::AK_ARMV8A, true },
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{ "cortex-a57", ARM::AK_ARMV8A, false },
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{ "cortex-a72", ARM::AK_ARMV8A, false },
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{ "cyclone", ARM::AK_ARMV8A, false },
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{ "generic", ARM::AK_ARMV8_1A, true },
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// Non-standard Arch names.
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{ "arm1022e", ARM::AK_ARMV5E, true },
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{ "arm926ej-s", ARM::AK_ARMV5TEJ, true },
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{ "cortex-m0", ARM::AK_ARMV6SM, true },
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{ "arm1176jzf-s", ARM::AK_ARMV6HL, true },
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{ "cortex-a8", ARM::AK_ARMV7L, true },
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{ "cortex-a8", ARM::AK_ARMV7HL, true },
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{ "cortex-m4", ARM::AK_ARMV7EM, true },
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{ "swift", ARM::AK_ARMV7S, true },
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// Invalid CPU
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{ "invalid", ARM::AK_INVALID, true }
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};
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} // namespace
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namespace llvm {
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// ======================================================= //
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// Information by ID
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// ======================================================= //
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const char *ARMTargetParser::getFPUName(unsigned FPUKind) {
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if (FPUKind >= ARM::FK_LAST)
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return nullptr;
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return FPUNames[FPUKind].Name;
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}
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const char *ARMTargetParser::getArchName(unsigned ArchKind) {
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if (ArchKind >= ARM::AK_LAST)
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return nullptr;
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return ARCHNames[ArchKind].Name;
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}
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const char *ARMTargetParser::getArchDefaultCPUName(unsigned ArchKind) {
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if (ArchKind >= ARM::AK_LAST)
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return nullptr;
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return ARCHNames[ArchKind].DefaultCPU;
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}
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unsigned ARMTargetParser::getArchDefaultCPUArch(unsigned ArchKind) {
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if (ArchKind >= ARM::AK_LAST)
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return ARMBuildAttrs::CPUArch::Pre_v4;
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return ARCHNames[ArchKind].DefaultArch;
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}
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const char *ARMTargetParser::getArchExtName(unsigned ArchExtKind) {
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if (ArchExtKind >= ARM::AEK_LAST)
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return nullptr;
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return ARCHExtNames[ArchExtKind].Name;
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}
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const char *ARMTargetParser::getDefaultCPU(StringRef Arch) {
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unsigned AK = parseArch(Arch);
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if (AK == ARM::AK_INVALID)
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return nullptr;
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// Look for multiple AKs to find the default for pair AK+Name.
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for (const auto CPU : CPUNames) {
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if (CPU.ArchID == AK && CPU.Default)
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return CPU.Name;
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}
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return nullptr;
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}
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// ======================================================= //
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// Parsers
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// ======================================================= //
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StringRef ARMTargetParser::getFPUSynonym(StringRef FPU) {
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return StringSwitch<StringRef>(FPU)
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.Cases("fpa", "fpe2", "fpe3", "maverick", "invalid") // Unsupported
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.Case("vfp2", "vfpv2")
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.Case("vfp3", "vfpv3")
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.Case("vfp4", "vfpv4")
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.Case("vfp3-d16", "vfpv3-d16")
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.Case("vfp4-d16", "vfpv4-d16")
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// FIXME: sp-16 is NOT the same as d16
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.Cases("fp4-sp-d16", "fpv4-sp-d16", "vfpv4-d16")
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.Cases("fp4-dp-d16", "fpv4-dp-d16", "vfpv4-d16")
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.Cases("fp5-sp-d16", "fpv5-sp-d16", "fpv5-d16")
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.Cases("fp5-dp-d16", "fpv5-dp-d16", "fpv5-d16")
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// FIXME: Clang uses it, but it's bogus, since neon defaults to vfpv3.
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.Case("neon-vfpv3", "neon")
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.Default(FPU);
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}
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StringRef ARMTargetParser::getArchSynonym(StringRef Arch) {
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return StringSwitch<StringRef>(Arch)
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.Cases("armv6m", "v6m", "armv6-m")
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.Cases("armv7a", "v7a", "armv7-a")
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.Cases("armv7r", "v7r", "armv7-r")
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.Cases("armv7m", "v7m", "armv7-m")
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.Cases("armv7em", "v7em", "armv7e-m")
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.Cases("armv8", "v8", "armv8-a")
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.Cases("armv8a", "v8a", "armv8-a")
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.Cases("armv8.1a", "v8.1a", "armv8.1-a")
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.Cases("aarch64", "arm64", "armv8-a")
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.Default(Arch);
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}
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// MArch is expected to be of the form (arm|thumb)?(eb)?(v.+)?(eb)?, but
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// (iwmmxt|xscale)(eb)? is also permitted. If the former, return
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// "v.+", if the latter, return unmodified string. If invalid, return "".
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StringRef ARMTargetParser::getCanonicalArchName(StringRef Arch) {
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size_t offset = StringRef::npos;
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StringRef A = Arch;
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StringRef Error = "";
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// Begins with "arm" / "thumb", move past it.
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if (A.startswith("arm"))
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offset = 3;
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else if (A.startswith("thumb"))
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offset = 5;
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else if (A.startswith("aarch64")) {
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offset = 7;
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// AArch64 uses "_be", not "eb" suffix.
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if (A.find("eb") != StringRef::npos)
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return Error;
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if (A.substr(offset,3) == "_be")
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offset += 3;
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}
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// Ex. "armebv7", move past the "eb".
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if (offset != StringRef::npos && A.substr(offset, 2) == "eb")
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offset += 2;
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// Or, if it ends with eb ("armv7eb"), chop it off.
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else if (A.endswith("eb"))
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A = A.substr(0, A.size() - 2);
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// Reached the end or a 'v', canonicalise.
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if (offset != StringRef::npos && (offset == A.size() || A[offset] == 'v'))
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A = A.substr(offset);
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// Empty string mans offset reached the end. Although valid, this arch
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// will not have a match in the table. Return the original string.
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if (A.empty())
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return Arch;
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// If can't find the arch, return an empty StringRef.
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if (parseArch(A) == ARM::AK_INVALID)
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return Error;
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// Arch will either be a 'v' name (v7a) or a marketing name (xscale)
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// or empty, if invalid.
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return A;
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}
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unsigned ARMTargetParser::parseFPU(StringRef FPU) {
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StringRef Syn = getFPUSynonym(FPU);
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for (const auto F : FPUNames) {
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if (Syn == F.Name)
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return F.ID;
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}
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return ARM::FK_INVALID;
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}
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// Allows partial match, ex. "v7a" matches "armv7a".
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unsigned ARMTargetParser::parseArch(StringRef Arch) {
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StringRef Syn = getArchSynonym(Arch);
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for (const auto A : ARCHNames) {
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if (StringRef(A.Name).endswith(Syn))
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return A.ID;
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}
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return ARM::AK_INVALID;
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}
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unsigned ARMTargetParser::parseArchExt(StringRef ArchExt) {
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for (const auto A : ARCHExtNames) {
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if (ArchExt == A.Name)
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return A.ID;
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}
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return ARM::AEK_INVALID;
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}
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unsigned ARMTargetParser::parseCPUArch(StringRef CPU) {
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for (const auto C : CPUNames) {
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if (CPU == C.Name)
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return C.ArchID;
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}
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return ARM::AK_INVALID;
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}
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// ARM, Thumb, AArch64
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unsigned ARMTargetParser::parseArchISA(StringRef Arch) {
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return StringSwitch<unsigned>(Arch)
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.StartsWith("aarch64", ARM::IK_AARCH64)
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.StartsWith("arm64", ARM::IK_AARCH64)
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.StartsWith("thumb", ARM::IK_THUMB)
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.StartsWith("arm", ARM::IK_ARM)
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.Default(ARM::EK_INVALID);
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}
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// Little/Big endian
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unsigned ARMTargetParser::parseArchEndian(StringRef Arch) {
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if (Arch.startswith("armeb") ||
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Arch.startswith("thumbeb") ||
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Arch.startswith("aarch64_be"))
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return ARM::EK_BIG;
|
|
|
|
if (Arch.startswith("arm") || Arch.startswith("thumb")) {
|
|
if (Arch.endswith("eb"))
|
|
return ARM::EK_BIG;
|
|
else
|
|
return ARM::EK_LITTLE;
|
|
}
|
|
|
|
if (Arch.startswith("aarch64"))
|
|
return ARM::EK_LITTLE;
|
|
|
|
return ARM::EK_INVALID;
|
|
}
|
|
|
|
} // namespace llvm
|