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https://github.com/c64scene-ar/llvm-6502.git
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ad249171e4
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@196102 91177308-0d34-0410-b5e6-96231b3b80d8
439 lines
19 KiB
C++
439 lines
19 KiB
C++
//===-- ARMBaseInstrInfo.h - ARM Base Instruction Information ---*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains the Base ARM implementation of the TargetInstrInfo class.
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//
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//===----------------------------------------------------------------------===//
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#ifndef ARMBASEINSTRUCTIONINFO_H
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#define ARMBASEINSTRUCTIONINFO_H
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#include "ARM.h"
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#include "llvm/ADT/DenseMap.h"
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#include "llvm/ADT/SmallSet.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/Target/TargetInstrInfo.h"
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#define GET_INSTRINFO_HEADER
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#include "ARMGenInstrInfo.inc"
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namespace llvm {
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class ARMSubtarget;
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class ARMBaseRegisterInfo;
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class ARMBaseInstrInfo : public ARMGenInstrInfo {
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const ARMSubtarget &Subtarget;
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protected:
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// Can be only subclassed.
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explicit ARMBaseInstrInfo(const ARMSubtarget &STI);
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public:
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// Return whether the target has an explicit NOP encoding.
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bool hasNOP() const;
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// Return the non-pre/post incrementing version of 'Opc'. Return 0
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// if there is not such an opcode.
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virtual unsigned getUnindexedOpcode(unsigned Opc) const =0;
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virtual MachineInstr *convertToThreeAddress(MachineFunction::iterator &MFI,
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MachineBasicBlock::iterator &MBBI,
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LiveVariables *LV) const;
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virtual const ARMBaseRegisterInfo &getRegisterInfo() const = 0;
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const ARMSubtarget &getSubtarget() const { return Subtarget; }
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ScheduleHazardRecognizer *
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CreateTargetHazardRecognizer(const TargetMachine *TM,
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const ScheduleDAG *DAG) const;
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ScheduleHazardRecognizer *
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CreateTargetPostRAHazardRecognizer(const InstrItineraryData *II,
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const ScheduleDAG *DAG) const;
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// Branch analysis.
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virtual bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
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MachineBasicBlock *&FBB,
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SmallVectorImpl<MachineOperand> &Cond,
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bool AllowModify = false) const;
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virtual unsigned RemoveBranch(MachineBasicBlock &MBB) const;
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virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
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MachineBasicBlock *FBB,
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const SmallVectorImpl<MachineOperand> &Cond,
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DebugLoc DL) const;
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virtual
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bool ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const;
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// Predication support.
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bool isPredicated(const MachineInstr *MI) const;
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ARMCC::CondCodes getPredicate(const MachineInstr *MI) const {
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int PIdx = MI->findFirstPredOperandIdx();
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return PIdx != -1 ? (ARMCC::CondCodes)MI->getOperand(PIdx).getImm()
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: ARMCC::AL;
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}
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virtual
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bool PredicateInstruction(MachineInstr *MI,
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const SmallVectorImpl<MachineOperand> &Pred) const;
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virtual
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bool SubsumesPredicate(const SmallVectorImpl<MachineOperand> &Pred1,
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const SmallVectorImpl<MachineOperand> &Pred2) const;
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virtual bool DefinesPredicate(MachineInstr *MI,
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std::vector<MachineOperand> &Pred) const;
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virtual bool isPredicable(MachineInstr *MI) const;
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/// GetInstSize - Returns the size of the specified MachineInstr.
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///
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virtual unsigned GetInstSizeInBytes(const MachineInstr* MI) const;
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virtual unsigned isLoadFromStackSlot(const MachineInstr *MI,
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int &FrameIndex) const;
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virtual unsigned isStoreToStackSlot(const MachineInstr *MI,
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int &FrameIndex) const;
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virtual unsigned isLoadFromStackSlotPostFE(const MachineInstr *MI,
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int &FrameIndex) const;
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virtual unsigned isStoreToStackSlotPostFE(const MachineInstr *MI,
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int &FrameIndex) const;
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virtual void copyPhysReg(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator I, DebugLoc DL,
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unsigned DestReg, unsigned SrcReg,
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bool KillSrc) const;
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virtual void storeRegToStackSlot(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MBBI,
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unsigned SrcReg, bool isKill, int FrameIndex,
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const TargetRegisterClass *RC,
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const TargetRegisterInfo *TRI) const;
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virtual void loadRegFromStackSlot(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MBBI,
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unsigned DestReg, int FrameIndex,
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const TargetRegisterClass *RC,
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const TargetRegisterInfo *TRI) const;
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virtual bool expandPostRAPseudo(MachineBasicBlock::iterator MI) const;
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virtual void reMaterialize(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MI,
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unsigned DestReg, unsigned SubIdx,
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const MachineInstr *Orig,
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const TargetRegisterInfo &TRI) const;
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MachineInstr *duplicate(MachineInstr *Orig, MachineFunction &MF) const;
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MachineInstr *commuteInstruction(MachineInstr*, bool=false) const;
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const MachineInstrBuilder &AddDReg(MachineInstrBuilder &MIB, unsigned Reg,
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unsigned SubIdx, unsigned State,
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const TargetRegisterInfo *TRI) const;
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virtual bool produceSameValue(const MachineInstr *MI0,
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const MachineInstr *MI1,
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const MachineRegisterInfo *MRI) const;
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/// areLoadsFromSameBasePtr - This is used by the pre-regalloc scheduler to
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/// determine if two loads are loading from the same base address. It should
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/// only return true if the base pointers are the same and the only
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/// differences between the two addresses is the offset. It also returns the
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/// offsets by reference.
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virtual bool areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2,
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int64_t &Offset1, int64_t &Offset2)const;
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/// shouldScheduleLoadsNear - This is a used by the pre-regalloc scheduler to
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/// determine (in conjunction with areLoadsFromSameBasePtr) if two loads
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/// should be scheduled togther. On some targets if two loads are loading from
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/// addresses in the same cache line, it's better if they are scheduled
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/// together. This function takes two integers that represent the load offsets
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/// from the common base address. It returns true if it decides it's desirable
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/// to schedule the two loads together. "NumLoads" is the number of loads that
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/// have already been scheduled after Load1.
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virtual bool shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2,
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int64_t Offset1, int64_t Offset2,
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unsigned NumLoads) const;
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virtual bool isSchedulingBoundary(const MachineInstr *MI,
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const MachineBasicBlock *MBB,
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const MachineFunction &MF) const;
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virtual bool isProfitableToIfCvt(MachineBasicBlock &MBB,
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unsigned NumCycles, unsigned ExtraPredCycles,
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const BranchProbability &Probability) const;
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virtual bool isProfitableToIfCvt(MachineBasicBlock &TMBB,
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unsigned NumT, unsigned ExtraT,
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MachineBasicBlock &FMBB,
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unsigned NumF, unsigned ExtraF,
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const BranchProbability &Probability) const;
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virtual bool isProfitableToDupForIfCvt(MachineBasicBlock &MBB,
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unsigned NumCycles,
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const BranchProbability
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&Probability) const {
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return NumCycles == 1;
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}
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virtual bool isProfitableToUnpredicate(MachineBasicBlock &TMBB,
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MachineBasicBlock &FMBB) const;
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/// analyzeCompare - For a comparison instruction, return the source registers
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/// in SrcReg and SrcReg2 if having two register operands, and the value it
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/// compares against in CmpValue. Return true if the comparison instruction
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/// can be analyzed.
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virtual bool analyzeCompare(const MachineInstr *MI, unsigned &SrcReg,
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unsigned &SrcReg2, int &CmpMask,
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int &CmpValue) const;
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/// optimizeCompareInstr - Convert the instruction to set the zero flag so
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/// that we can remove a "comparison with zero"; Remove a redundant CMP
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/// instruction if the flags can be updated in the same way by an earlier
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/// instruction such as SUB.
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virtual bool optimizeCompareInstr(MachineInstr *CmpInstr, unsigned SrcReg,
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unsigned SrcReg2, int CmpMask, int CmpValue,
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const MachineRegisterInfo *MRI) const;
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virtual bool analyzeSelect(const MachineInstr *MI,
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SmallVectorImpl<MachineOperand> &Cond,
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unsigned &TrueOp, unsigned &FalseOp,
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bool &Optimizable) const;
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virtual MachineInstr *optimizeSelect(MachineInstr *MI, bool) const;
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/// FoldImmediate - 'Reg' is known to be defined by a move immediate
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/// instruction, try to fold the immediate into the use instruction.
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virtual bool FoldImmediate(MachineInstr *UseMI, MachineInstr *DefMI,
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unsigned Reg, MachineRegisterInfo *MRI) const;
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virtual unsigned getNumMicroOps(const InstrItineraryData *ItinData,
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const MachineInstr *MI) const;
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virtual
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int getOperandLatency(const InstrItineraryData *ItinData,
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const MachineInstr *DefMI, unsigned DefIdx,
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const MachineInstr *UseMI, unsigned UseIdx) const;
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virtual
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int getOperandLatency(const InstrItineraryData *ItinData,
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SDNode *DefNode, unsigned DefIdx,
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SDNode *UseNode, unsigned UseIdx) const;
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/// VFP/NEON execution domains.
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std::pair<uint16_t, uint16_t>
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getExecutionDomain(const MachineInstr *MI) const;
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void setExecutionDomain(MachineInstr *MI, unsigned Domain) const;
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unsigned getPartialRegUpdateClearance(const MachineInstr*, unsigned,
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const TargetRegisterInfo*) const;
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void breakPartialRegDependency(MachineBasicBlock::iterator, unsigned,
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const TargetRegisterInfo *TRI) const;
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/// Get the number of addresses by LDM or VLDM or zero for unknown.
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unsigned getNumLDMAddresses(const MachineInstr *MI) const;
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private:
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unsigned getInstBundleLength(const MachineInstr *MI) const;
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int getVLDMDefCycle(const InstrItineraryData *ItinData,
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const MCInstrDesc &DefMCID,
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unsigned DefClass,
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unsigned DefIdx, unsigned DefAlign) const;
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int getLDMDefCycle(const InstrItineraryData *ItinData,
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const MCInstrDesc &DefMCID,
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unsigned DefClass,
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unsigned DefIdx, unsigned DefAlign) const;
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int getVSTMUseCycle(const InstrItineraryData *ItinData,
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const MCInstrDesc &UseMCID,
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unsigned UseClass,
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unsigned UseIdx, unsigned UseAlign) const;
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int getSTMUseCycle(const InstrItineraryData *ItinData,
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const MCInstrDesc &UseMCID,
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unsigned UseClass,
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unsigned UseIdx, unsigned UseAlign) const;
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int getOperandLatency(const InstrItineraryData *ItinData,
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const MCInstrDesc &DefMCID,
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unsigned DefIdx, unsigned DefAlign,
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const MCInstrDesc &UseMCID,
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unsigned UseIdx, unsigned UseAlign) const;
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unsigned getPredicationCost(const MachineInstr *MI) const;
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unsigned getInstrLatency(const InstrItineraryData *ItinData,
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const MachineInstr *MI,
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unsigned *PredCost = 0) const;
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int getInstrLatency(const InstrItineraryData *ItinData,
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SDNode *Node) const;
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bool hasHighOperandLatency(const InstrItineraryData *ItinData,
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const MachineRegisterInfo *MRI,
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const MachineInstr *DefMI, unsigned DefIdx,
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const MachineInstr *UseMI, unsigned UseIdx) const;
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bool hasLowDefLatency(const InstrItineraryData *ItinData,
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const MachineInstr *DefMI, unsigned DefIdx) const;
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/// verifyInstruction - Perform target specific instruction verification.
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bool verifyInstruction(const MachineInstr *MI, StringRef &ErrInfo) const;
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private:
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/// Modeling special VFP / NEON fp MLA / MLS hazards.
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/// MLxEntryMap - Map fp MLA / MLS to the corresponding entry in the internal
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/// MLx table.
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DenseMap<unsigned, unsigned> MLxEntryMap;
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/// MLxHazardOpcodes - Set of add / sub and multiply opcodes that would cause
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/// stalls when scheduled together with fp MLA / MLS opcodes.
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SmallSet<unsigned, 16> MLxHazardOpcodes;
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public:
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/// isFpMLxInstruction - Return true if the specified opcode is a fp MLA / MLS
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/// instruction.
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bool isFpMLxInstruction(unsigned Opcode) const {
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return MLxEntryMap.count(Opcode);
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}
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/// isFpMLxInstruction - This version also returns the multiply opcode and the
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/// addition / subtraction opcode to expand to. Return true for 'HasLane' for
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/// the MLX instructions with an extra lane operand.
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bool isFpMLxInstruction(unsigned Opcode, unsigned &MulOpc,
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unsigned &AddSubOpc, bool &NegAcc,
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bool &HasLane) const;
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/// canCauseFpMLxStall - Return true if an instruction of the specified opcode
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/// will cause stalls when scheduled after (within 4-cycle window) a fp
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/// MLA / MLS instruction.
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bool canCauseFpMLxStall(unsigned Opcode) const {
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return MLxHazardOpcodes.count(Opcode);
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}
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/// Returns true if the instruction has a shift by immediate that can be
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/// executed in one cycle less.
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bool isSwiftFastImmShift(const MachineInstr *MI) const;
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};
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static inline
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const MachineInstrBuilder &AddDefaultPred(const MachineInstrBuilder &MIB) {
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return MIB.addImm((int64_t)ARMCC::AL).addReg(0);
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}
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static inline
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const MachineInstrBuilder &AddDefaultCC(const MachineInstrBuilder &MIB) {
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return MIB.addReg(0);
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}
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static inline
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const MachineInstrBuilder &AddDefaultT1CC(const MachineInstrBuilder &MIB,
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bool isDead = false) {
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return MIB.addReg(ARM::CPSR, getDefRegState(true) | getDeadRegState(isDead));
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}
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static inline
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const MachineInstrBuilder &AddNoT1CC(const MachineInstrBuilder &MIB) {
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return MIB.addReg(0);
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}
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static inline
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bool isUncondBranchOpcode(int Opc) {
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return Opc == ARM::B || Opc == ARM::tB || Opc == ARM::t2B;
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}
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static inline
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bool isCondBranchOpcode(int Opc) {
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return Opc == ARM::Bcc || Opc == ARM::tBcc || Opc == ARM::t2Bcc;
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}
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static inline
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bool isJumpTableBranchOpcode(int Opc) {
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return Opc == ARM::BR_JTr || Opc == ARM::BR_JTm || Opc == ARM::BR_JTadd ||
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Opc == ARM::tBR_JTr || Opc == ARM::t2BR_JT;
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}
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static inline
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bool isIndirectBranchOpcode(int Opc) {
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return Opc == ARM::BX || Opc == ARM::MOVPCRX || Opc == ARM::tBRIND;
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}
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static inline bool isPopOpcode(int Opc) {
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return Opc == ARM::tPOP_RET || Opc == ARM::LDMIA_RET ||
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Opc == ARM::t2LDMIA_RET || Opc == ARM::tPOP || Opc == ARM::LDMIA_UPD ||
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Opc == ARM::t2LDMIA_UPD || Opc == ARM::VLDMDIA_UPD;
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}
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static inline bool isPushOpcode(int Opc) {
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return Opc == ARM::tPUSH || Opc == ARM::t2STMDB_UPD ||
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Opc == ARM::STMDB_UPD || Opc == ARM::VSTMDDB_UPD;
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}
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/// getInstrPredicate - If instruction is predicated, returns its predicate
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/// condition, otherwise returns AL. It also returns the condition code
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/// register by reference.
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ARMCC::CondCodes getInstrPredicate(const MachineInstr *MI, unsigned &PredReg);
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int getMatchingCondBranchOpcode(int Opc);
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/// Determine if MI can be folded into an ARM MOVCC instruction, and return the
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/// opcode of the SSA instruction representing the conditional MI.
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unsigned canFoldARMInstrIntoMOVCC(unsigned Reg,
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MachineInstr *&MI,
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const MachineRegisterInfo &MRI);
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/// Map pseudo instructions that imply an 'S' bit onto real opcodes. Whether
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/// the instruction is encoded with an 'S' bit is determined by the optional
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/// CPSR def operand.
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unsigned convertAddSubFlagsOpcode(unsigned OldOpc);
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/// emitARMRegPlusImmediate / emitT2RegPlusImmediate - Emits a series of
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/// instructions to materializea destreg = basereg + immediate in ARM / Thumb2
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/// code.
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void emitARMRegPlusImmediate(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator &MBBI, DebugLoc dl,
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unsigned DestReg, unsigned BaseReg, int NumBytes,
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ARMCC::CondCodes Pred, unsigned PredReg,
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const ARMBaseInstrInfo &TII, unsigned MIFlags = 0);
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void emitT2RegPlusImmediate(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator &MBBI, DebugLoc dl,
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unsigned DestReg, unsigned BaseReg, int NumBytes,
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ARMCC::CondCodes Pred, unsigned PredReg,
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const ARMBaseInstrInfo &TII, unsigned MIFlags = 0);
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void emitThumbRegPlusImmediate(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator &MBBI, DebugLoc dl,
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unsigned DestReg, unsigned BaseReg,
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int NumBytes, const TargetInstrInfo &TII,
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const ARMBaseRegisterInfo& MRI,
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unsigned MIFlags = 0);
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/// Tries to add registers to the reglist of a given base-updating
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/// push/pop instruction to adjust the stack by an additional
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/// NumBytes. This can save a few bytes per function in code-size, but
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/// obviously generates more memory traffic. As such, it only takes
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/// effect in functions being optimised for size.
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bool tryFoldSPUpdateIntoPushPop(const ARMSubtarget &Subtarget,
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MachineFunction &MF, MachineInstr *MI,
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unsigned NumBytes);
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/// rewriteARMFrameIndex / rewriteT2FrameIndex -
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/// Rewrite MI to access 'Offset' bytes from the FP. Return false if the
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/// offset could not be handled directly in MI, and return the left-over
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/// portion by reference.
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bool rewriteARMFrameIndex(MachineInstr &MI, unsigned FrameRegIdx,
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unsigned FrameReg, int &Offset,
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const ARMBaseInstrInfo &TII);
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bool rewriteT2FrameIndex(MachineInstr &MI, unsigned FrameRegIdx,
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unsigned FrameReg, int &Offset,
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const ARMBaseInstrInfo &TII);
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} // End llvm namespace
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#endif
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