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80683c0be6
Summary: Generate one DSLL32 of 0 instead of two consecutive DSLL of 16. In order to do this I had to change createLShiftOri's template argument from a bool to an unsigned. This also gave me the opportunity to rewrite the mips64-expansions.s test, as it was testing the same cases multiple times and skipping over other cases. It was also somewhat unreadable, as the CHECK lines were grouped in a huge block of text at the beginning of the file. Reviewers: dsanders Reviewed By: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D8974 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@236311 91177308-0d34-0410-b5e6-96231b3b80d8 |
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Analysis | ||
AsmParser | ||
Bitcode | ||
CodeGen | ||
DebugInfo | ||
ExecutionEngine | ||
Fuzzer | ||
IR | ||
IRReader | ||
LineEditor | ||
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LTO | ||
MC | ||
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ProfileData | ||
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TableGen | ||
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CMakeLists.txt | ||
LLVMBuild.txt | ||
Makefile |