llvm-6502

mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2025-01-30 19:35:54 +00:00

History

Toma Tabacu 80683c0be6 [mips] [IAS] Slightly improve shift instruction generation in expandLoadImm.

Summary:
Generate one DSLL32 of 0 instead of two consecutive DSLL of 16.
In order to do this I had to change createLShiftOri's template argument from a bool to an unsigned.

This also gave me the opportunity to rewrite the mips64-expansions.s test, as it was testing the same cases multiple times and skipping over other cases.
It was also somewhat unreadable, as the CHECK lines were grouped in a huge block of text at the beginning of the file.

Reviewers: dsanders

Reviewed By: dsanders

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D8974

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@236311 91177308-0d34-0410-b5e6-96231b3b80d8

2015-05-01 10:26:47 +00:00

Analysis

Fix -Wpessimizing-move warnings by removing std::move calls.

2015-04-30 23:07:00 +00:00

AsmParser

[opaque pointer type] Pass GlobalAlias the actual pointer type rather than decomposing it into pointee type + address space

2015-04-29 21:22:39 +00:00

Bitcode

Don't overflow GCTable

2015-04-30 04:09:41 +00:00

CodeGen

[SelectionDAG] Unary vector constant folding integer legality fixes