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llvm-6502/test/MC/Disassembler/X86
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Craig Topper 95717dbb11 [X86] Fix a bug where the disassembler was ignoring the VEX.W bit in 32-bit mode for certain instructions it shouldn't. 
Unfortunately, this isn't easy to fix since there's no simple way to figure out from the disassembler tables whether the W-bit is being used to select a 64-bit GPR or if its a required part of the opcode. The fix implemented here just looks for "64" in the instruction name and ignores the W-bit in 32-bit mode if its present.

Fixes PR21169.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@219194 91177308-0d34-0410-b5e6-96231b3b80d8
2014-10-07 07:29:50 +00:00
..
avx-512.txt [X86] AVX512: Add disassembler support for compressed displacement 2014-07-17 17:04:56 +00:00
fp-stack.txt Add two fp test cases I missed in my previous commit. 2013-12-31 23:15:19 +00:00
hex-immediates.txt llvm-mc: Add option for prefering hex format disassembly. 2014-06-11 20:26:40 +00:00
intel-syntax-32.txt First round of fixes for the x86 fixes for the x86 move accumulator from/to memory offset instructions. 2013-08-25 22:23:38 +00:00
intel-syntax.txt Fixing Intel format of the vshufpd instruction. 2013-09-27 01:44:23 +00:00
invalid-cmp-imm.txt
invalid-VEX-vvvv.txt
lit.local.cfg Reduce verbiage of lit.local.cfg files 2014-06-09 22:42:55 +00:00
marked-up.txt
missing-sib.txt Test case for r204305. 2014-03-20 06:45:10 +00:00
moffs.txt llvm-mc: Add option for prefering hex format disassembly. 2014-06-11 20:26:40 +00:00
padlock.txt Remove A6/A7 opcode maps. They can all be handled with a TB map, opcode of 0xa6/0xa7, and adding MRM_C0/MRM_E0 forms. Removes 376K from the disassembler tables. 2014-02-19 05:34:21 +00:00
prefixes.txt X86Disassembler - fixed a bug in immediate print 2014-04-23 07:21:04 +00:00
simple-tests.txt Remove need for MODIFIER_OPCODE in the disassembler tables. AddRegFrms are really more like OrRegFrm so we don't need a difference since we can just mask bits. 2014-01-01 15:29:32 +00:00
truncated-input.txt
x86-16.txt [x86] Fix 16-bit disassembly of JCXZ/JECXZ 2014-01-20 12:02:48 +00:00
x86-32.txt [X86] Fix a bug where the disassembler was ignoring the VEX.W bit in 32-bit mode for certain instructions it shouldn't. 2014-10-07 07:29:50 +00:00
x86-64.txt Fix diassembler handling of rex.b when mod=00/01/10 and bbb=101. Mod=00 should ignore the base register entirely. Mod=01/10 should treat this as R13 plus displacment. Fixes PR18860. 2014-02-17 10:03:43 +00:00