mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-08-24 09:29:42 +00:00
fe2b8b1960
Summary: ... and after all that refactoring, it's possible to distinguish softfloat floating point values from integers so this patch no longer breaks softfloat to do it. Remove direct handling of i32's in the N32/N64 ABI by promoting them to i64. This more closely reflects the ABI documentation and also fixes problems with stack arguments on big-endian targets. We now rely on signext/zeroext annotations (already generated by clang) and the Assert[SZ]ext nodes to avoid the introduction of unnecessary sign/zero extends. It was not possible to convert three tests to use signext/zeroext. These tests are bswap.ll, ctlz-v.ll, ctlz-v.ll. It's not possible to put signext on a vector type so we just accept the sign extends here for now. These tests don't pass the vectors the same way clang does (clang puts multiple elements in the same argument, these map 1 element to 1 argument) so we don't need to worry too much about it. With this patch, all known N32/N64 bugs should be fixed and we now pass the first 10,000 tests generated by ABITest.py. Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D6117 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@221534 91177308-0d34-0410-b5e6-96231b3b80d8
517 lines
23 KiB
TableGen
517 lines
23 KiB
TableGen
//===- Mips64InstrInfo.td - Mips64 Instruction Information -*- tablegen -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file describes Mips64 instructions.
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//
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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// Mips Operand, Complex Patterns and Transformations Definitions.
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//===----------------------------------------------------------------------===//
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// Unsigned Operand
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def uimm16_64 : Operand<i64> {
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let PrintMethod = "printUnsignedImm";
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}
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// Signed Operand
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def simm10_64 : Operand<i64>;
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def imm64: Operand<i64>;
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// Transformation Function - get Imm - 32.
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def Subtract32 : SDNodeXForm<imm, [{
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return getImm(N, (unsigned)N->getZExtValue() - 32);
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}]>;
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// shamt must fit in 6 bits.
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def immZExt6 : ImmLeaf<i32, [{return Imm == (Imm & 0x3f);}]>;
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// Node immediate fits as 10-bit sign extended on target immediate.
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// e.g. seqi, snei
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def immSExt10_64 : PatLeaf<(i64 imm),
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[{ return isInt<10>(N->getSExtValue()); }]>;
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def immZExt16_64 : PatLeaf<(i64 imm),
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[{ return isInt<16>(N->getZExtValue()); }]>;
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//===----------------------------------------------------------------------===//
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// Instructions specific format
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//===----------------------------------------------------------------------===//
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let usesCustomInserter = 1 in {
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def ATOMIC_LOAD_ADD_I64 : Atomic2Ops<atomic_load_add_64, GPR64>;
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def ATOMIC_LOAD_SUB_I64 : Atomic2Ops<atomic_load_sub_64, GPR64>;
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def ATOMIC_LOAD_AND_I64 : Atomic2Ops<atomic_load_and_64, GPR64>;
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def ATOMIC_LOAD_OR_I64 : Atomic2Ops<atomic_load_or_64, GPR64>;
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def ATOMIC_LOAD_XOR_I64 : Atomic2Ops<atomic_load_xor_64, GPR64>;
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def ATOMIC_LOAD_NAND_I64 : Atomic2Ops<atomic_load_nand_64, GPR64>;
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def ATOMIC_SWAP_I64 : Atomic2Ops<atomic_swap_64, GPR64>;
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def ATOMIC_CMP_SWAP_I64 : AtomicCmpSwap<atomic_cmp_swap_64, GPR64>;
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}
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/// Pseudo instructions for loading and storing accumulator registers.
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let isPseudo = 1, isCodeGenOnly = 1 in {
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def LOAD_ACC128 : Load<"", ACC128>;
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def STORE_ACC128 : Store<"", ACC128>;
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}
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//===----------------------------------------------------------------------===//
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// Instruction definition
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//===----------------------------------------------------------------------===//
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let DecoderNamespace = "Mips64" in {
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/// Arithmetic Instructions (ALU Immediate)
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def DADDi : ArithLogicI<"daddi", simm16_64, GPR64Opnd>, ADDI_FM<0x18>,
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ISA_MIPS3_NOT_32R6_64R6;
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def DADDiu : ArithLogicI<"daddiu", simm16_64, GPR64Opnd, II_DADDIU,
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immSExt16, add>,
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ADDI_FM<0x19>, IsAsCheapAsAMove, ISA_MIPS3;
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let isCodeGenOnly = 1 in {
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def SLTi64 : SetCC_I<"slti", setlt, simm16_64, immSExt16, GPR64Opnd>,
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SLTI_FM<0xa>;
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def SLTiu64 : SetCC_I<"sltiu", setult, simm16_64, immSExt16, GPR64Opnd>,
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SLTI_FM<0xb>;
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def ANDi64 : ArithLogicI<"andi", uimm16_64, GPR64Opnd, II_AND, immZExt16, and>,
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ADDI_FM<0xc>;
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def ORi64 : ArithLogicI<"ori", uimm16_64, GPR64Opnd, II_OR, immZExt16, or>,
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ADDI_FM<0xd>;
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def XORi64 : ArithLogicI<"xori", uimm16_64, GPR64Opnd, II_XOR, immZExt16, xor>,
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ADDI_FM<0xe>;
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def LUi64 : LoadUpper<"lui", GPR64Opnd, uimm16_64>, LUI_FM;
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}
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/// Arithmetic Instructions (3-Operand, R-Type)
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def DADD : ArithLogicR<"dadd", GPR64Opnd, 1, II_DADD>, ADD_FM<0, 0x2c>,
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ISA_MIPS3;
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def DADDu : ArithLogicR<"daddu", GPR64Opnd, 1, II_DADDU, add>, ADD_FM<0, 0x2d>,
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ISA_MIPS3;
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def DSUBu : ArithLogicR<"dsubu", GPR64Opnd, 0, II_DSUBU, sub>, ADD_FM<0, 0x2f>,
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ISA_MIPS3;
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def DSUB : ArithLogicR<"dsub", GPR64Opnd, 0, II_DSUB>, ADD_FM<0, 0x2e>,
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ISA_MIPS3;
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let isCodeGenOnly = 1 in {
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def SLT64 : SetCC_R<"slt", setlt, GPR64Opnd>, ADD_FM<0, 0x2a>;
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def SLTu64 : SetCC_R<"sltu", setult, GPR64Opnd>, ADD_FM<0, 0x2b>;
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def AND64 : ArithLogicR<"and", GPR64Opnd, 1, II_AND, and>, ADD_FM<0, 0x24>;
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def OR64 : ArithLogicR<"or", GPR64Opnd, 1, II_OR, or>, ADD_FM<0, 0x25>;
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def XOR64 : ArithLogicR<"xor", GPR64Opnd, 1, II_XOR, xor>, ADD_FM<0, 0x26>;
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def NOR64 : LogicNOR<"nor", GPR64Opnd>, ADD_FM<0, 0x27>;
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}
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/// Shift Instructions
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def DSLL : shift_rotate_imm<"dsll", uimm6, GPR64Opnd, II_DSLL, shl, immZExt6>,
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SRA_FM<0x38, 0>, ISA_MIPS3;
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def DSRL : shift_rotate_imm<"dsrl", uimm6, GPR64Opnd, II_DSRL, srl, immZExt6>,
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SRA_FM<0x3a, 0>, ISA_MIPS3;
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def DSRA : shift_rotate_imm<"dsra", uimm6, GPR64Opnd, II_DSRA, sra, immZExt6>,
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SRA_FM<0x3b, 0>, ISA_MIPS3;
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def DSLLV : shift_rotate_reg<"dsllv", GPR64Opnd, II_DSLLV, shl>,
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SRLV_FM<0x14, 0>, ISA_MIPS3;
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def DSRLV : shift_rotate_reg<"dsrlv", GPR64Opnd, II_DSRLV, srl>,
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SRLV_FM<0x16, 0>, ISA_MIPS3;
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def DSRAV : shift_rotate_reg<"dsrav", GPR64Opnd, II_DSRAV, sra>,
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SRLV_FM<0x17, 0>, ISA_MIPS3;
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def DSLL32 : shift_rotate_imm<"dsll32", uimm5, GPR64Opnd, II_DSLL32>,
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SRA_FM<0x3c, 0>, ISA_MIPS3;
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def DSRL32 : shift_rotate_imm<"dsrl32", uimm5, GPR64Opnd, II_DSRL32>,
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SRA_FM<0x3e, 0>, ISA_MIPS3;
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def DSRA32 : shift_rotate_imm<"dsra32", uimm5, GPR64Opnd, II_DSRA32>,
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SRA_FM<0x3f, 0>, ISA_MIPS3;
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// Rotate Instructions
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def DROTR : shift_rotate_imm<"drotr", uimm6, GPR64Opnd, II_DROTR, rotr,
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immZExt6>,
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SRA_FM<0x3a, 1>, ISA_MIPS64R2;
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def DROTRV : shift_rotate_reg<"drotrv", GPR64Opnd, II_DROTRV, rotr>,
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SRLV_FM<0x16, 1>, ISA_MIPS64R2;
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def DROTR32 : shift_rotate_imm<"drotr32", uimm5, GPR64Opnd, II_DROTR32>,
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SRA_FM<0x3e, 1>, ISA_MIPS64R2;
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/// Load and Store Instructions
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/// aligned
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let isCodeGenOnly = 1 in {
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def LB64 : Load<"lb", GPR64Opnd, sextloadi8, II_LB>, LW_FM<0x20>;
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def LBu64 : Load<"lbu", GPR64Opnd, zextloadi8, II_LBU>, LW_FM<0x24>;
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def LH64 : Load<"lh", GPR64Opnd, sextloadi16, II_LH>, LW_FM<0x21>;
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def LHu64 : Load<"lhu", GPR64Opnd, zextloadi16, II_LHU>, LW_FM<0x25>;
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def LW64 : Load<"lw", GPR64Opnd, sextloadi32, II_LW>, LW_FM<0x23>;
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def SB64 : Store<"sb", GPR64Opnd, truncstorei8, II_SB>, LW_FM<0x28>;
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def SH64 : Store<"sh", GPR64Opnd, truncstorei16, II_SH>, LW_FM<0x29>;
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def SW64 : Store<"sw", GPR64Opnd, truncstorei32, II_SW>, LW_FM<0x2b>;
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}
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def LWu : Load<"lwu", GPR64Opnd, zextloadi32, II_LWU>, LW_FM<0x27>, ISA_MIPS3;
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def LD : Load<"ld", GPR64Opnd, load, II_LD>, LW_FM<0x37>, ISA_MIPS3;
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def SD : Store<"sd", GPR64Opnd, store, II_SD>, LW_FM<0x3f>, ISA_MIPS3;
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/// load/store left/right
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let isCodeGenOnly = 1 in {
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def LWL64 : LoadLeftRight<"lwl", MipsLWL, GPR64Opnd, II_LWL>, LW_FM<0x22>;
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def LWR64 : LoadLeftRight<"lwr", MipsLWR, GPR64Opnd, II_LWR>, LW_FM<0x26>;
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def SWL64 : StoreLeftRight<"swl", MipsSWL, GPR64Opnd, II_SWL>, LW_FM<0x2a>;
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def SWR64 : StoreLeftRight<"swr", MipsSWR, GPR64Opnd, II_SWR>, LW_FM<0x2e>;
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}
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def LDL : LoadLeftRight<"ldl", MipsLDL, GPR64Opnd, II_LDL>, LW_FM<0x1a>,
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ISA_MIPS3_NOT_32R6_64R6;
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def LDR : LoadLeftRight<"ldr", MipsLDR, GPR64Opnd, II_LDR>, LW_FM<0x1b>,
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ISA_MIPS3_NOT_32R6_64R6;
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def SDL : StoreLeftRight<"sdl", MipsSDL, GPR64Opnd, II_SDL>, LW_FM<0x2c>,
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ISA_MIPS3_NOT_32R6_64R6;
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def SDR : StoreLeftRight<"sdr", MipsSDR, GPR64Opnd, II_SDR>, LW_FM<0x2d>,
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ISA_MIPS3_NOT_32R6_64R6;
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/// Load-linked, Store-conditional
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def LLD : LLBase<"lld", GPR64Opnd>, LW_FM<0x34>, ISA_MIPS3_NOT_32R6_64R6;
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def SCD : SCBase<"scd", GPR64Opnd>, LW_FM<0x3c>, ISA_MIPS3_NOT_32R6_64R6;
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/// Jump and Branch Instructions
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let isCodeGenOnly = 1 in {
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def JR64 : IndirectBranch<"jr", GPR64Opnd>, MTLO_FM<8>;
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def BEQ64 : CBranch<"beq", brtarget, seteq, GPR64Opnd>, BEQ_FM<4>;
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def BNE64 : CBranch<"bne", brtarget, setne, GPR64Opnd>, BEQ_FM<5>;
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def BGEZ64 : CBranchZero<"bgez", brtarget, setge, GPR64Opnd>, BGEZ_FM<1, 1>;
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def BGTZ64 : CBranchZero<"bgtz", brtarget, setgt, GPR64Opnd>, BGEZ_FM<7, 0>;
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def BLEZ64 : CBranchZero<"blez", brtarget, setle, GPR64Opnd>, BGEZ_FM<6, 0>;
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def BLTZ64 : CBranchZero<"bltz", brtarget, setlt, GPR64Opnd>, BGEZ_FM<1, 0>;
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def JALR64 : JumpLinkReg<"jalr", GPR64Opnd>, JALR_FM;
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def JALR64Pseudo : JumpLinkRegPseudo<GPR64Opnd, JALR, RA, GPR32Opnd>;
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def TAILCALL64_R : TailCallReg<GPR64Opnd, JR, GPR32Opnd>;
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}
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def PseudoReturn64 : PseudoReturnBase<GPR64Opnd>;
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def PseudoIndirectBranch64 : PseudoIndirectBranchBase<GPR64Opnd>;
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/// Multiply and Divide Instructions.
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def DMULT : Mult<"dmult", II_DMULT, GPR64Opnd, [HI0_64, LO0_64]>,
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MULT_FM<0, 0x1c>, ISA_MIPS3_NOT_32R6_64R6;
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def DMULTu : Mult<"dmultu", II_DMULTU, GPR64Opnd, [HI0_64, LO0_64]>,
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MULT_FM<0, 0x1d>, ISA_MIPS3_NOT_32R6_64R6;
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def PseudoDMULT : MultDivPseudo<DMULT, ACC128, GPR64Opnd, MipsMult,
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II_DMULT>, ISA_MIPS3_NOT_32R6_64R6;
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def PseudoDMULTu : MultDivPseudo<DMULTu, ACC128, GPR64Opnd, MipsMultu,
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II_DMULTU>, ISA_MIPS3_NOT_32R6_64R6;
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def DSDIV : Div<"ddiv", II_DDIV, GPR64Opnd, [HI0_64, LO0_64]>,
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MULT_FM<0, 0x1e>, ISA_MIPS3_NOT_32R6_64R6;
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def DUDIV : Div<"ddivu", II_DDIVU, GPR64Opnd, [HI0_64, LO0_64]>,
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MULT_FM<0, 0x1f>, ISA_MIPS3_NOT_32R6_64R6;
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def PseudoDSDIV : MultDivPseudo<DSDIV, ACC128, GPR64Opnd, MipsDivRem,
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II_DDIV, 0, 1, 1>, ISA_MIPS3_NOT_32R6_64R6;
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def PseudoDUDIV : MultDivPseudo<DUDIV, ACC128, GPR64Opnd, MipsDivRemU,
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II_DDIVU, 0, 1, 1>, ISA_MIPS3_NOT_32R6_64R6;
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let isCodeGenOnly = 1 in {
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def MTHI64 : MoveToLOHI<"mthi", GPR64Opnd, [HI0_64]>, MTLO_FM<0x11>,
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ISA_MIPS3_NOT_32R6_64R6;
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def MTLO64 : MoveToLOHI<"mtlo", GPR64Opnd, [LO0_64]>, MTLO_FM<0x13>,
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ISA_MIPS3_NOT_32R6_64R6;
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def MFHI64 : MoveFromLOHI<"mfhi", GPR64Opnd, AC0_64>, MFLO_FM<0x10>,
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ISA_MIPS3_NOT_32R6_64R6;
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def MFLO64 : MoveFromLOHI<"mflo", GPR64Opnd, AC0_64>, MFLO_FM<0x12>,
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ISA_MIPS3_NOT_32R6_64R6;
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def PseudoMFHI64 : PseudoMFLOHI<GPR64, ACC128, MipsMFHI>,
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ISA_MIPS3_NOT_32R6_64R6;
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def PseudoMFLO64 : PseudoMFLOHI<GPR64, ACC128, MipsMFLO>,
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ISA_MIPS3_NOT_32R6_64R6;
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def PseudoMTLOHI64 : PseudoMTLOHI<ACC128, GPR64>, ISA_MIPS3_NOT_32R6_64R6;
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/// Sign Ext In Register Instructions.
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def SEB64 : SignExtInReg<"seb", i8, GPR64Opnd, II_SEB>, SEB_FM<0x10, 0x20>,
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ISA_MIPS32R2;
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def SEH64 : SignExtInReg<"seh", i16, GPR64Opnd, II_SEH>, SEB_FM<0x18, 0x20>,
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ISA_MIPS32R2;
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}
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/// Count Leading
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def DCLZ : CountLeading0<"dclz", GPR64Opnd>, CLO_FM<0x24>, ISA_MIPS64_NOT_64R6;
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def DCLO : CountLeading1<"dclo", GPR64Opnd>, CLO_FM<0x25>, ISA_MIPS64_NOT_64R6;
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/// Double Word Swap Bytes/HalfWords
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def DSBH : SubwordSwap<"dsbh", GPR64Opnd>, SEB_FM<2, 0x24>, ISA_MIPS64R2;
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def DSHD : SubwordSwap<"dshd", GPR64Opnd>, SEB_FM<5, 0x24>, ISA_MIPS64R2;
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def LEA_ADDiu64 : EffectiveAddress<"daddiu", GPR64Opnd>, LW_FM<0x19>;
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let isCodeGenOnly = 1 in
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def RDHWR64 : ReadHardware<GPR64Opnd, HWRegsOpnd>, RDHWR_FM;
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def DEXT : ExtBase<"dext", GPR64Opnd, uimm6, MipsExt>, EXT_FM<3>;
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def DEXTU : ExtBase<"dextu", GPR64Opnd, uimm6>, EXT_FM<2>;
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def DEXTM : ExtBase<"dextm", GPR64Opnd, uimm5>, EXT_FM<1>;
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def DINS : InsBase<"dins", GPR64Opnd, uimm6, MipsIns>, EXT_FM<7>;
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def DINSU : InsBase<"dinsu", GPR64Opnd, uimm6>, EXT_FM<6>;
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def DINSM : InsBase<"dinsm", GPR64Opnd, uimm5>, EXT_FM<5>;
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let isCodeGenOnly = 1, rs = 0, shamt = 0 in {
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def DSLL64_32 : FR<0x00, 0x3c, (outs GPR64:$rd), (ins GPR32:$rt),
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"dsll\t$rd, $rt, 32", [], II_DSLL>;
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def SLL64_32 : FR<0x0, 0x00, (outs GPR64:$rd), (ins GPR32:$rt),
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"sll\t$rd, $rt, 0", [], II_SLL>;
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def SLL64_64 : FR<0x0, 0x00, (outs GPR64:$rd), (ins GPR64:$rt),
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"sll\t$rd, $rt, 0", [], II_SLL>;
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}
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// We need the following pseudo instruction to avoid offset calculation for
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// long branches. See the comment in file MipsLongBranch.cpp for detailed
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// explanation.
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// Expands to: daddiu $dst, $src, %PART($tgt - $baltgt)
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// where %PART may be %hi or %lo, depending on the relocation kind
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// that $tgt is annotated with.
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def LONG_BRANCH_DADDiu : PseudoSE<(outs GPR64Opnd:$dst),
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(ins GPR64Opnd:$src, brtarget:$tgt, brtarget:$baltgt), []>;
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// Cavium Octeon cmMIPS instructions
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let EncodingPredicates = []<Predicate>, // FIXME: The lack of HasStdEnc is probably a bug
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AdditionalPredicates = [HasCnMips] in {
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class Count1s<string opstr, RegisterOperand RO>:
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InstSE<(outs RO:$rd), (ins RO:$rs), !strconcat(opstr, "\t$rd, $rs"),
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[(set RO:$rd, (ctpop RO:$rs))], II_POP, FrmR, opstr> {
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let TwoOperandAliasConstraint = "$rd = $rs";
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}
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class ExtsCins<string opstr, SDPatternOperator Op = null_frag>:
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InstSE<(outs GPR64Opnd:$rt), (ins GPR64Opnd:$rs, uimm5:$pos, uimm5:$lenm1),
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!strconcat(opstr, " $rt, $rs, $pos, $lenm1"),
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[(set GPR64Opnd:$rt, (Op GPR64Opnd:$rs, imm:$pos, imm:$lenm1))],
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NoItinerary, FrmR, opstr> {
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let TwoOperandAliasConstraint = "$rt = $rs";
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}
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class SetCC64_R<string opstr, PatFrag cond_op> :
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InstSE<(outs GPR64Opnd:$rd), (ins GPR64Opnd:$rs, GPR64Opnd:$rt),
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!strconcat(opstr, "\t$rd, $rs, $rt"),
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[(set GPR64Opnd:$rd, (cond_op GPR64Opnd:$rs, GPR64Opnd:$rt))],
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II_SEQ_SNE, FrmR, opstr> {
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let TwoOperandAliasConstraint = "$rd = $rs";
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}
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class SetCC64_I<string opstr, PatFrag cond_op>:
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InstSE<(outs GPR64Opnd:$rt), (ins GPR64Opnd:$rs, simm10_64:$imm10),
|
|
!strconcat(opstr, "\t$rt, $rs, $imm10"),
|
|
[(set GPR64Opnd:$rt, (cond_op GPR64Opnd:$rs, immSExt10_64:$imm10))],
|
|
II_SEQI_SNEI, FrmI, opstr> {
|
|
let TwoOperandAliasConstraint = "$rt = $rs";
|
|
}
|
|
|
|
// Unsigned Byte Add
|
|
let Pattern = [(set GPR64Opnd:$rd,
|
|
(and (add GPR64Opnd:$rs, GPR64Opnd:$rt), 255))] in
|
|
def BADDu : ArithLogicR<"baddu", GPR64Opnd, 1, II_BADDU>,
|
|
ADD_FM<0x1c, 0x28>;
|
|
|
|
// Multiply Doubleword to GPR
|
|
let Defs = [HI0, LO0, P0, P1, P2] in
|
|
def DMUL : ArithLogicR<"dmul", GPR64Opnd, 1, II_DMUL, mul>,
|
|
ADD_FM<0x1c, 0x03>;
|
|
|
|
// Extract a signed bit field /+32
|
|
def EXTS : ExtsCins<"exts">, EXTS_FM<0x3a>;
|
|
def EXTS32: ExtsCins<"exts32">, EXTS_FM<0x3b>;
|
|
|
|
// Clear and insert a bit field /+32
|
|
def CINS : ExtsCins<"cins">, EXTS_FM<0x32>;
|
|
def CINS32: ExtsCins<"cins32">, EXTS_FM<0x33>;
|
|
|
|
// Move to multiplier/product register
|
|
def MTM0 : MoveToLOHI<"mtm0", GPR64Opnd, [MPL0, P0, P1, P2]>, MTMR_FM<0x08>;
|
|
def MTM1 : MoveToLOHI<"mtm1", GPR64Opnd, [MPL1, P0, P1, P2]>, MTMR_FM<0x0c>;
|
|
def MTM2 : MoveToLOHI<"mtm2", GPR64Opnd, [MPL2, P0, P1, P2]>, MTMR_FM<0x0d>;
|
|
def MTP0 : MoveToLOHI<"mtp0", GPR64Opnd, [P0]>, MTMR_FM<0x09>;
|
|
def MTP1 : MoveToLOHI<"mtp1", GPR64Opnd, [P1]>, MTMR_FM<0x0a>;
|
|
def MTP2 : MoveToLOHI<"mtp2", GPR64Opnd, [P2]>, MTMR_FM<0x0b>;
|
|
|
|
// Count Ones in a Word/Doubleword
|
|
def POP : Count1s<"pop", GPR32Opnd>, POP_FM<0x2c>;
|
|
def DPOP : Count1s<"dpop", GPR64Opnd>, POP_FM<0x2d>;
|
|
|
|
// Set on equal/not equal
|
|
def SEQ : SetCC64_R<"seq", seteq>, SEQ_FM<0x2a>;
|
|
def SEQi : SetCC64_I<"seqi", seteq>, SEQI_FM<0x2e>;
|
|
def SNE : SetCC64_R<"sne", setne>, SEQ_FM<0x2b>;
|
|
def SNEi : SetCC64_I<"snei", setne>, SEQI_FM<0x2f>;
|
|
|
|
// 192-bit x 64-bit Unsigned Multiply and Add
|
|
let Defs = [P0, P1, P2] in
|
|
def V3MULU: ArithLogicR<"v3mulu", GPR64Opnd, 0, II_DMUL>,
|
|
ADD_FM<0x1c, 0x11>;
|
|
|
|
// 64-bit Unsigned Multiply and Add Move
|
|
let Defs = [MPL0, P0, P1, P2] in
|
|
def VMM0 : ArithLogicR<"vmm0", GPR64Opnd, 0, II_DMUL>,
|
|
ADD_FM<0x1c, 0x10>;
|
|
|
|
// 64-bit Unsigned Multiply and Add
|
|
let Defs = [MPL1, MPL2, P0, P1, P2] in
|
|
def VMULU : ArithLogicR<"vmulu", GPR64Opnd, 0, II_DMUL>,
|
|
ADD_FM<0x1c, 0x0f>;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// Arbitrary patterns that map to one or more instructions
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
// extended loads
|
|
def : MipsPat<(i64 (extloadi1 addr:$src)), (LB64 addr:$src)>;
|
|
def : MipsPat<(i64 (extloadi8 addr:$src)), (LB64 addr:$src)>;
|
|
def : MipsPat<(i64 (extloadi16 addr:$src)), (LH64 addr:$src)>;
|
|
def : MipsPat<(i64 (extloadi32 addr:$src)), (LW64 addr:$src)>;
|
|
|
|
// hi/lo relocs
|
|
def : MipsPat<(MipsHi tglobaladdr:$in), (LUi64 tglobaladdr:$in)>;
|
|
def : MipsPat<(MipsHi tblockaddress:$in), (LUi64 tblockaddress:$in)>;
|
|
def : MipsPat<(MipsHi tjumptable:$in), (LUi64 tjumptable:$in)>;
|
|
def : MipsPat<(MipsHi tconstpool:$in), (LUi64 tconstpool:$in)>;
|
|
def : MipsPat<(MipsHi tglobaltlsaddr:$in), (LUi64 tglobaltlsaddr:$in)>;
|
|
def : MipsPat<(MipsHi texternalsym:$in), (LUi64 texternalsym:$in)>;
|
|
|
|
def : MipsPat<(MipsLo tglobaladdr:$in), (DADDiu ZERO_64, tglobaladdr:$in)>;
|
|
def : MipsPat<(MipsLo tblockaddress:$in), (DADDiu ZERO_64, tblockaddress:$in)>;
|
|
def : MipsPat<(MipsLo tjumptable:$in), (DADDiu ZERO_64, tjumptable:$in)>;
|
|
def : MipsPat<(MipsLo tconstpool:$in), (DADDiu ZERO_64, tconstpool:$in)>;
|
|
def : MipsPat<(MipsLo tglobaltlsaddr:$in),
|
|
(DADDiu ZERO_64, tglobaltlsaddr:$in)>;
|
|
def : MipsPat<(MipsLo texternalsym:$in), (DADDiu ZERO_64, texternalsym:$in)>;
|
|
|
|
def : MipsPat<(add GPR64:$hi, (MipsLo tglobaladdr:$lo)),
|
|
(DADDiu GPR64:$hi, tglobaladdr:$lo)>;
|
|
def : MipsPat<(add GPR64:$hi, (MipsLo tblockaddress:$lo)),
|
|
(DADDiu GPR64:$hi, tblockaddress:$lo)>;
|
|
def : MipsPat<(add GPR64:$hi, (MipsLo tjumptable:$lo)),
|
|
(DADDiu GPR64:$hi, tjumptable:$lo)>;
|
|
def : MipsPat<(add GPR64:$hi, (MipsLo tconstpool:$lo)),
|
|
(DADDiu GPR64:$hi, tconstpool:$lo)>;
|
|
def : MipsPat<(add GPR64:$hi, (MipsLo tglobaltlsaddr:$lo)),
|
|
(DADDiu GPR64:$hi, tglobaltlsaddr:$lo)>;
|
|
|
|
def : WrapperPat<tglobaladdr, DADDiu, GPR64>;
|
|
def : WrapperPat<tconstpool, DADDiu, GPR64>;
|
|
def : WrapperPat<texternalsym, DADDiu, GPR64>;
|
|
def : WrapperPat<tblockaddress, DADDiu, GPR64>;
|
|
def : WrapperPat<tjumptable, DADDiu, GPR64>;
|
|
def : WrapperPat<tglobaltlsaddr, DADDiu, GPR64>;
|
|
|
|
defm : BrcondPats<GPR64, BEQ64, BNE64, SLT64, SLTu64, SLTi64, SLTiu64,
|
|
ZERO_64>;
|
|
|
|
def : MipsPat<(brcond (i32 (setlt i64:$lhs, 1)), bb:$dst),
|
|
(BLEZ64 i64:$lhs, bb:$dst)>;
|
|
def : MipsPat<(brcond (i32 (setgt i64:$lhs, -1)), bb:$dst),
|
|
(BGEZ64 i64:$lhs, bb:$dst)>;
|
|
|
|
// setcc patterns
|
|
defm : SeteqPats<GPR64, SLTiu64, XOR64, SLTu64, ZERO_64>;
|
|
defm : SetlePats<GPR64, SLT64, SLTu64>;
|
|
defm : SetgtPats<GPR64, SLT64, SLTu64>;
|
|
defm : SetgePats<GPR64, SLT64, SLTu64>;
|
|
defm : SetgeImmPats<GPR64, SLTi64, SLTiu64>;
|
|
|
|
// truncate
|
|
def : MipsPat<(trunc (assertsext GPR64:$src)),
|
|
(EXTRACT_SUBREG GPR64:$src, sub_32)>;
|
|
def : MipsPat<(trunc (assertzext GPR64:$src)),
|
|
(EXTRACT_SUBREG GPR64:$src, sub_32)>;
|
|
def : MipsPat<(i32 (trunc GPR64:$src)),
|
|
(SLL (EXTRACT_SUBREG GPR64:$src, sub_32), 0)>;
|
|
|
|
// 32-to-64-bit extension
|
|
def : MipsPat<(i64 (anyext GPR32:$src)), (SLL64_32 GPR32:$src)>;
|
|
def : MipsPat<(i64 (zext GPR32:$src)), (DSRL (DSLL64_32 GPR32:$src), 32)>;
|
|
def : MipsPat<(i64 (sext GPR32:$src)), (SLL64_32 GPR32:$src)>;
|
|
|
|
// Sign extend in register
|
|
def : MipsPat<(i64 (sext_inreg GPR64:$src, i32)),
|
|
(SLL64_64 GPR64:$src)>;
|
|
|
|
// bswap MipsPattern
|
|
def : MipsPat<(bswap GPR64:$rt), (DSHD (DSBH GPR64:$rt))>;
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// Instruction aliases
|
|
//===----------------------------------------------------------------------===//
|
|
def : MipsInstAlias<"move $dst, $src",
|
|
(DADDu GPR64Opnd:$dst, GPR64Opnd:$src, ZERO_64), 1>,
|
|
GPR_64;
|
|
def : MipsInstAlias<"daddu $rs, $rt, $imm",
|
|
(DADDiu GPR64Opnd:$rs, GPR64Opnd:$rt, simm16_64:$imm),
|
|
0>, ISA_MIPS3;
|
|
def : MipsInstAlias<"dadd $rs, $rt, $imm",
|
|
(DADDi GPR64Opnd:$rs, GPR64Opnd:$rt, simm16_64:$imm),
|
|
0>, ISA_MIPS3_NOT_32R6_64R6;
|
|
def : MipsInstAlias<"daddu $rs, $imm",
|
|
(DADDiu GPR64Opnd:$rs, GPR64Opnd:$rs, simm16_64:$imm),
|
|
0>, ISA_MIPS3;
|
|
def : MipsInstAlias<"dadd $rs, $imm",
|
|
(DADDi GPR64Opnd:$rs, GPR64Opnd:$rs, simm16_64:$imm),
|
|
0>, ISA_MIPS3_NOT_32R6_64R6;
|
|
def : MipsInstAlias<"dsll $rd, $rt, $rs",
|
|
(DSLLV GPR64Opnd:$rd, GPR64Opnd:$rt, GPR32Opnd:$rs), 0>,
|
|
ISA_MIPS3;
|
|
def : MipsInstAlias<"dsubu $rt, $rs, $imm",
|
|
(DADDiu GPR64Opnd:$rt, GPR64Opnd:$rs,
|
|
InvertedImOperand64:$imm), 0>, ISA_MIPS3;
|
|
def : MipsInstAlias<"dsubi $rs, $rt, $imm",
|
|
(DADDi GPR64Opnd:$rs, GPR64Opnd:$rt,
|
|
InvertedImOperand64:$imm),
|
|
0>, ISA_MIPS3_NOT_32R6_64R6;
|
|
def : MipsInstAlias<"dsubi $rs, $imm",
|
|
(DADDi GPR64Opnd:$rs, GPR64Opnd:$rs,
|
|
InvertedImOperand64:$imm),
|
|
0>, ISA_MIPS3_NOT_32R6_64R6;
|
|
def : MipsInstAlias<"dsub $rs, $rt, $imm",
|
|
(DADDi GPR64Opnd:$rs, GPR64Opnd:$rt,
|
|
InvertedImOperand64:$imm),
|
|
0>, ISA_MIPS3_NOT_32R6_64R6;
|
|
def : MipsInstAlias<"dsub $rs, $imm",
|
|
(DADDi GPR64Opnd:$rs, GPR64Opnd:$rs,
|
|
InvertedImOperand64:$imm),
|
|
0>, ISA_MIPS3_NOT_32R6_64R6;
|
|
def : MipsInstAlias<"dsubu $rs, $imm",
|
|
(DADDiu GPR64Opnd:$rs, GPR64Opnd:$rs,
|
|
InvertedImOperand64:$imm),
|
|
0>, ISA_MIPS3;
|
|
def : MipsInstAlias<"dsra $rd, $rt, $rs",
|
|
(DSRAV GPR64Opnd:$rd, GPR64Opnd:$rt, GPR32Opnd:$rs), 0>,
|
|
ISA_MIPS3;
|
|
def : MipsInstAlias<"dsrl $rd, $rt, $rs",
|
|
(DSRLV GPR64Opnd:$rd, GPR64Opnd:$rt, GPR32Opnd:$rs), 0>,
|
|
ISA_MIPS3;
|
|
|
|
class LoadImm64< string instr_asm, Operand Od, RegisterOperand RO> :
|
|
MipsAsmPseudoInst<(outs RO:$rt), (ins Od:$imm64),
|
|
!strconcat(instr_asm, "\t$rt, $imm64")> ;
|
|
def LoadImm64Reg : LoadImm64<"dli", imm64, GPR64Opnd>;
|
|
|
|
/// Move between CPU and coprocessor registers
|
|
let DecoderNamespace = "Mips64", Predicates = [HasMips64] in {
|
|
def DMFC0 : MFC3OP<"dmfc0", GPR64Opnd>, MFC3OP_FM<0x10, 1>;
|
|
def DMTC0 : MFC3OP<"dmtc0", GPR64Opnd>, MFC3OP_FM<0x10, 5>, ISA_MIPS3;
|
|
def DMFC2 : MFC3OP<"dmfc2", GPR64Opnd>, MFC3OP_FM<0x12, 1>, ISA_MIPS3;
|
|
def DMTC2 : MFC3OP<"dmtc2", GPR64Opnd>, MFC3OP_FM<0x12, 5>, ISA_MIPS3;
|
|
}
|
|
|
|
// Two operand (implicit 0 selector) versions:
|
|
def : MipsInstAlias<"dmfc0 $rt, $rd", (DMFC0 GPR64Opnd:$rt, GPR64Opnd:$rd, 0), 0>;
|
|
def : MipsInstAlias<"dmtc0 $rt, $rd", (DMTC0 GPR64Opnd:$rt, GPR64Opnd:$rd, 0), 0>;
|
|
def : MipsInstAlias<"dmfc2 $rt, $rd", (DMFC2 GPR64Opnd:$rt, GPR64Opnd:$rd, 0), 0>;
|
|
def : MipsInstAlias<"dmtc2 $rt, $rd", (DMTC2 GPR64Opnd:$rt, GPR64Opnd:$rd, 0), 0>;
|
|
|
|
let Predicates = [HasMips64, HasCnMips] in {
|
|
def : MipsInstAlias<"synciobdma", (SYNC 0x2), 0>;
|
|
def : MipsInstAlias<"syncs", (SYNC 0x6), 0>;
|
|
def : MipsInstAlias<"syncw", (SYNC 0x4), 0>;
|
|
def : MipsInstAlias<"syncws", (SYNC 0x5), 0>;
|
|
}
|