mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-12-15 20:29:48 +00:00
8eaed0f63d
This matches the format produced by the AMD proprietary driver.
//==================================================================//
// Shell script for converting .ll test cases: (Pass the .ll files
you want to convert to this script as arguments).
//==================================================================//
; This was necessary on my system so that A-Z in sed would match only
; upper case. I'm not sure why.
export LC_ALL='C'
TEST_FILES="$*"
MATCHES=`grep -v Patterns SIInstructions.td | grep -o '"[A-Z0-9_]\+["e]' | grep -o '[A-Z0-9_]\+' | sort -r`
for f in $TEST_FILES; do
# Check that there are SI tests:
grep -q -e 'verde' -e 'bonaire' -e 'SI' -e 'tahiti' $f
if [ $? -eq 0 ]; then
for match in $MATCHES; do
sed -i -e "s/\([ :]$match\)/\L\1/" $f
done
# Try to get check lines with partial instruction names
sed -i 's/\(;[ ]*SI[A-Z\\-]*: \)\([A-Z_0-9]\+\)/\1\L\2/' $f
fi
done
sed -i -e 's/bb0_1/BB0_1/g' ../../../test/CodeGen/R600/infinite-loop.ll
sed -i -e 's/SI-NOT: bfe/SI-NOT: {{[^@]}}bfe/g'../../../test/CodeGen/R600/llvm.AMDGPU.bfe.*32.ll ../../../test/CodeGen/R600/sext-in-reg.ll
sed -i -e 's/exp_IEEE/EXP_IEEE/g' ../../../test/CodeGen/R600/llvm.exp2.ll
sed -i -e 's/numVgprs/NumVgprs/g' ../../../test/CodeGen/R600/register-count-comments.ll
sed -i 's/\(; CHECK[-NOT]*: \)\([A-Z_0-9]\+\)/\1\L\2/' ../../../test/CodeGen/R600/select64.ll ../../../test/CodeGen/R600/sgpr-copy.ll
//==================================================================//
// Shell script for converting .td files (run this last)
//==================================================================//
export LC_ALL='C'
sed -i -e '/Patterns/!s/\("[A-Z0-9_]\+[ "e]\)/\L\1/g' SIInstructions.td
sed -i -e 's/"EXP/"exp/g' SIInstrInfo.td
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@221350 91177308-0d34-0410-b5e6-96231b3b80d8
509 lines
28 KiB
LLVM
509 lines
28 KiB
LLVM
;RUN: llc < %s -march=r600 -mcpu=verde -verify-machineinstrs | FileCheck %s
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;CHECK-LABEL: {{^}}gather4_v2:
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;CHECK: image_gather4 {{v\[[0-9]+:[0-9]+\]}}, 1, 0, 0, -1, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}
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define void @gather4_v2() #0 {
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main_body:
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%r = call <4 x float> @llvm.SI.gather4.v2i32(<2 x i32> undef, <32 x i8> undef, <16 x i8> undef, i32 1, i32 0, i32 0, i32 1, i32 0, i32 0, i32 0, i32 0)
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%r0 = extractelement <4 x float> %r, i32 0
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%r1 = extractelement <4 x float> %r, i32 1
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%r2 = extractelement <4 x float> %r, i32 2
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%r3 = extractelement <4 x float> %r, i32 3
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call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %r0, float %r1, float %r2, float %r3)
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ret void
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}
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;CHECK-LABEL: {{^}}gather4:
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;CHECK: image_gather4 {{v\[[0-9]+:[0-9]+\]}}, 1, 0, 0, -1, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}
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define void @gather4() #0 {
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main_body:
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%r = call <4 x float> @llvm.SI.gather4.v4i32(<4 x i32> undef, <32 x i8> undef, <16 x i8> undef, i32 1, i32 0, i32 0, i32 1, i32 0, i32 0, i32 0, i32 0)
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%r0 = extractelement <4 x float> %r, i32 0
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%r1 = extractelement <4 x float> %r, i32 1
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%r2 = extractelement <4 x float> %r, i32 2
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%r3 = extractelement <4 x float> %r, i32 3
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call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %r0, float %r1, float %r2, float %r3)
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ret void
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}
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;CHECK-LABEL: {{^}}gather4_cl:
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;CHECK: image_gather4_cl {{v\[[0-9]+:[0-9]+\]}}, 1, 0, 0, -1, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}
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define void @gather4_cl() #0 {
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main_body:
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%r = call <4 x float> @llvm.SI.gather4.cl.v4i32(<4 x i32> undef, <32 x i8> undef, <16 x i8> undef, i32 1, i32 0, i32 0, i32 1, i32 0, i32 0, i32 0, i32 0)
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%r0 = extractelement <4 x float> %r, i32 0
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%r1 = extractelement <4 x float> %r, i32 1
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%r2 = extractelement <4 x float> %r, i32 2
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%r3 = extractelement <4 x float> %r, i32 3
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call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %r0, float %r1, float %r2, float %r3)
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ret void
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}
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;CHECK-LABEL: {{^}}gather4_l:
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;CHECK: image_gather4_l {{v\[[0-9]+:[0-9]+\]}}, 1, 0, 0, -1, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}
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define void @gather4_l() #0 {
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main_body:
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%r = call <4 x float> @llvm.SI.gather4.l.v4i32(<4 x i32> undef, <32 x i8> undef, <16 x i8> undef, i32 1, i32 0, i32 0, i32 1, i32 0, i32 0, i32 0, i32 0)
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%r0 = extractelement <4 x float> %r, i32 0
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%r1 = extractelement <4 x float> %r, i32 1
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%r2 = extractelement <4 x float> %r, i32 2
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%r3 = extractelement <4 x float> %r, i32 3
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call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %r0, float %r1, float %r2, float %r3)
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ret void
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}
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;CHECK-LABEL: {{^}}gather4_b:
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;CHECK: image_gather4_b {{v\[[0-9]+:[0-9]+\]}}, 1, 0, 0, -1, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}
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define void @gather4_b() #0 {
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main_body:
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%r = call <4 x float> @llvm.SI.gather4.b.v4i32(<4 x i32> undef, <32 x i8> undef, <16 x i8> undef, i32 1, i32 0, i32 0, i32 1, i32 0, i32 0, i32 0, i32 0)
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%r0 = extractelement <4 x float> %r, i32 0
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%r1 = extractelement <4 x float> %r, i32 1
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%r2 = extractelement <4 x float> %r, i32 2
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%r3 = extractelement <4 x float> %r, i32 3
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call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %r0, float %r1, float %r2, float %r3)
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ret void
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}
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;CHECK-LABEL: {{^}}gather4_b_cl:
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;CHECK: image_gather4_b_cl {{v\[[0-9]+:[0-9]+\]}}, 1, 0, 0, -1, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}
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define void @gather4_b_cl() #0 {
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main_body:
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%r = call <4 x float> @llvm.SI.gather4.b.cl.v4i32(<4 x i32> undef, <32 x i8> undef, <16 x i8> undef, i32 1, i32 0, i32 0, i32 1, i32 0, i32 0, i32 0, i32 0)
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%r0 = extractelement <4 x float> %r, i32 0
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%r1 = extractelement <4 x float> %r, i32 1
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%r2 = extractelement <4 x float> %r, i32 2
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%r3 = extractelement <4 x float> %r, i32 3
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call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %r0, float %r1, float %r2, float %r3)
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ret void
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}
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;CHECK-LABEL: {{^}}gather4_b_cl_v8:
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;CHECK: image_gather4_b_cl {{v\[[0-9]+:[0-9]+\]}}, 1, 0, 0, -1, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}
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define void @gather4_b_cl_v8() #0 {
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main_body:
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%r = call <4 x float> @llvm.SI.gather4.b.cl.v8i32(<8 x i32> undef, <32 x i8> undef, <16 x i8> undef, i32 1, i32 0, i32 0, i32 1, i32 0, i32 0, i32 0, i32 0)
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%r0 = extractelement <4 x float> %r, i32 0
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%r1 = extractelement <4 x float> %r, i32 1
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%r2 = extractelement <4 x float> %r, i32 2
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%r3 = extractelement <4 x float> %r, i32 3
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call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %r0, float %r1, float %r2, float %r3)
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ret void
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}
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;CHECK-LABEL: {{^}}gather4_lz_v2:
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;CHECK: image_gather4_lz {{v\[[0-9]+:[0-9]+\]}}, 1, 0, 0, -1, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}
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define void @gather4_lz_v2() #0 {
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main_body:
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%r = call <4 x float> @llvm.SI.gather4.lz.v2i32(<2 x i32> undef, <32 x i8> undef, <16 x i8> undef, i32 1, i32 0, i32 0, i32 1, i32 0, i32 0, i32 0, i32 0)
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%r0 = extractelement <4 x float> %r, i32 0
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%r1 = extractelement <4 x float> %r, i32 1
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%r2 = extractelement <4 x float> %r, i32 2
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%r3 = extractelement <4 x float> %r, i32 3
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call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %r0, float %r1, float %r2, float %r3)
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ret void
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}
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;CHECK-LABEL: {{^}}gather4_lz:
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;CHECK: image_gather4_lz {{v\[[0-9]+:[0-9]+\]}}, 1, 0, 0, -1, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}
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define void @gather4_lz() #0 {
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main_body:
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%r = call <4 x float> @llvm.SI.gather4.lz.v4i32(<4 x i32> undef, <32 x i8> undef, <16 x i8> undef, i32 1, i32 0, i32 0, i32 1, i32 0, i32 0, i32 0, i32 0)
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%r0 = extractelement <4 x float> %r, i32 0
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%r1 = extractelement <4 x float> %r, i32 1
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%r2 = extractelement <4 x float> %r, i32 2
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%r3 = extractelement <4 x float> %r, i32 3
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call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %r0, float %r1, float %r2, float %r3)
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ret void
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}
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;CHECK-LABEL: {{^}}gather4_o:
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;CHECK: image_gather4_o {{v\[[0-9]+:[0-9]+\]}}, 1, 0, 0, -1, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}
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define void @gather4_o() #0 {
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main_body:
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%r = call <4 x float> @llvm.SI.gather4.o.v4i32(<4 x i32> undef, <32 x i8> undef, <16 x i8> undef, i32 1, i32 0, i32 0, i32 1, i32 0, i32 0, i32 0, i32 0)
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%r0 = extractelement <4 x float> %r, i32 0
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%r1 = extractelement <4 x float> %r, i32 1
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%r2 = extractelement <4 x float> %r, i32 2
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%r3 = extractelement <4 x float> %r, i32 3
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call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %r0, float %r1, float %r2, float %r3)
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ret void
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}
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;CHECK-LABEL: {{^}}gather4_cl_o:
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;CHECK: image_gather4_cl_o {{v\[[0-9]+:[0-9]+\]}}, 1, 0, 0, -1, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}
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define void @gather4_cl_o() #0 {
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main_body:
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%r = call <4 x float> @llvm.SI.gather4.cl.o.v4i32(<4 x i32> undef, <32 x i8> undef, <16 x i8> undef, i32 1, i32 0, i32 0, i32 1, i32 0, i32 0, i32 0, i32 0)
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%r0 = extractelement <4 x float> %r, i32 0
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%r1 = extractelement <4 x float> %r, i32 1
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%r2 = extractelement <4 x float> %r, i32 2
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%r3 = extractelement <4 x float> %r, i32 3
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call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %r0, float %r1, float %r2, float %r3)
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ret void
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}
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;CHECK-LABEL: {{^}}gather4_cl_o_v8:
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;CHECK: image_gather4_cl_o {{v\[[0-9]+:[0-9]+\]}}, 1, 0, 0, -1, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}
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define void @gather4_cl_o_v8() #0 {
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main_body:
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%r = call <4 x float> @llvm.SI.gather4.cl.o.v8i32(<8 x i32> undef, <32 x i8> undef, <16 x i8> undef, i32 1, i32 0, i32 0, i32 1, i32 0, i32 0, i32 0, i32 0)
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%r0 = extractelement <4 x float> %r, i32 0
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%r1 = extractelement <4 x float> %r, i32 1
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%r2 = extractelement <4 x float> %r, i32 2
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%r3 = extractelement <4 x float> %r, i32 3
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call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %r0, float %r1, float %r2, float %r3)
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ret void
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}
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;CHECK-LABEL: {{^}}gather4_l_o:
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;CHECK: image_gather4_l_o {{v\[[0-9]+:[0-9]+\]}}, 1, 0, 0, -1, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}
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define void @gather4_l_o() #0 {
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main_body:
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%r = call <4 x float> @llvm.SI.gather4.l.o.v4i32(<4 x i32> undef, <32 x i8> undef, <16 x i8> undef, i32 1, i32 0, i32 0, i32 1, i32 0, i32 0, i32 0, i32 0)
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%r0 = extractelement <4 x float> %r, i32 0
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%r1 = extractelement <4 x float> %r, i32 1
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%r2 = extractelement <4 x float> %r, i32 2
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%r3 = extractelement <4 x float> %r, i32 3
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call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %r0, float %r1, float %r2, float %r3)
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ret void
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}
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;CHECK-LABEL: {{^}}gather4_l_o_v8:
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;CHECK: image_gather4_l_o {{v\[[0-9]+:[0-9]+\]}}, 1, 0, 0, -1, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}
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define void @gather4_l_o_v8() #0 {
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main_body:
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%r = call <4 x float> @llvm.SI.gather4.l.o.v8i32(<8 x i32> undef, <32 x i8> undef, <16 x i8> undef, i32 1, i32 0, i32 0, i32 1, i32 0, i32 0, i32 0, i32 0)
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%r0 = extractelement <4 x float> %r, i32 0
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%r1 = extractelement <4 x float> %r, i32 1
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%r2 = extractelement <4 x float> %r, i32 2
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%r3 = extractelement <4 x float> %r, i32 3
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call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %r0, float %r1, float %r2, float %r3)
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ret void
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}
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;CHECK-LABEL: {{^}}gather4_b_o:
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;CHECK: image_gather4_b_o {{v\[[0-9]+:[0-9]+\]}}, 1, 0, 0, -1, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}
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define void @gather4_b_o() #0 {
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main_body:
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%r = call <4 x float> @llvm.SI.gather4.b.o.v4i32(<4 x i32> undef, <32 x i8> undef, <16 x i8> undef, i32 1, i32 0, i32 0, i32 1, i32 0, i32 0, i32 0, i32 0)
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%r0 = extractelement <4 x float> %r, i32 0
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%r1 = extractelement <4 x float> %r, i32 1
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%r2 = extractelement <4 x float> %r, i32 2
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%r3 = extractelement <4 x float> %r, i32 3
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call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %r0, float %r1, float %r2, float %r3)
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ret void
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}
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;CHECK-LABEL: {{^}}gather4_b_o_v8:
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;CHECK: image_gather4_b_o {{v\[[0-9]+:[0-9]+\]}}, 1, 0, 0, -1, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}
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define void @gather4_b_o_v8() #0 {
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main_body:
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%r = call <4 x float> @llvm.SI.gather4.b.o.v8i32(<8 x i32> undef, <32 x i8> undef, <16 x i8> undef, i32 1, i32 0, i32 0, i32 1, i32 0, i32 0, i32 0, i32 0)
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%r0 = extractelement <4 x float> %r, i32 0
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%r1 = extractelement <4 x float> %r, i32 1
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%r2 = extractelement <4 x float> %r, i32 2
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%r3 = extractelement <4 x float> %r, i32 3
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call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %r0, float %r1, float %r2, float %r3)
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ret void
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}
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;CHECK-LABEL: {{^}}gather4_b_cl_o:
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;CHECK: image_gather4_b_cl_o {{v\[[0-9]+:[0-9]+\]}}, 1, 0, 0, -1, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}
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define void @gather4_b_cl_o() #0 {
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main_body:
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%r = call <4 x float> @llvm.SI.gather4.b.cl.o.v8i32(<8 x i32> undef, <32 x i8> undef, <16 x i8> undef, i32 1, i32 0, i32 0, i32 1, i32 0, i32 0, i32 0, i32 0)
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%r0 = extractelement <4 x float> %r, i32 0
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%r1 = extractelement <4 x float> %r, i32 1
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%r2 = extractelement <4 x float> %r, i32 2
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%r3 = extractelement <4 x float> %r, i32 3
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call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %r0, float %r1, float %r2, float %r3)
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ret void
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}
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;CHECK-LABEL: {{^}}gather4_lz_o:
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;CHECK: image_gather4_lz_o {{v\[[0-9]+:[0-9]+\]}}, 1, 0, 0, -1, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}
|
|
define void @gather4_lz_o() #0 {
|
|
main_body:
|
|
%r = call <4 x float> @llvm.SI.gather4.lz.o.v4i32(<4 x i32> undef, <32 x i8> undef, <16 x i8> undef, i32 1, i32 0, i32 0, i32 1, i32 0, i32 0, i32 0, i32 0)
|
|
%r0 = extractelement <4 x float> %r, i32 0
|
|
%r1 = extractelement <4 x float> %r, i32 1
|
|
%r2 = extractelement <4 x float> %r, i32 2
|
|
%r3 = extractelement <4 x float> %r, i32 3
|
|
call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %r0, float %r1, float %r2, float %r3)
|
|
ret void
|
|
}
|
|
|
|
|
|
|
|
;CHECK-LABEL: {{^}}gather4_c:
|
|
;CHECK: image_gather4_c {{v\[[0-9]+:[0-9]+\]}}, 1, 0, 0, -1, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}
|
|
define void @gather4_c() #0 {
|
|
main_body:
|
|
%r = call <4 x float> @llvm.SI.gather4.c.v4i32(<4 x i32> undef, <32 x i8> undef, <16 x i8> undef, i32 1, i32 0, i32 0, i32 1, i32 0, i32 0, i32 0, i32 0)
|
|
%r0 = extractelement <4 x float> %r, i32 0
|
|
%r1 = extractelement <4 x float> %r, i32 1
|
|
%r2 = extractelement <4 x float> %r, i32 2
|
|
%r3 = extractelement <4 x float> %r, i32 3
|
|
call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %r0, float %r1, float %r2, float %r3)
|
|
ret void
|
|
}
|
|
|
|
;CHECK-LABEL: {{^}}gather4_c_cl:
|
|
;CHECK: image_gather4_c_cl {{v\[[0-9]+:[0-9]+\]}}, 1, 0, 0, -1, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}
|
|
define void @gather4_c_cl() #0 {
|
|
main_body:
|
|
%r = call <4 x float> @llvm.SI.gather4.c.cl.v4i32(<4 x i32> undef, <32 x i8> undef, <16 x i8> undef, i32 1, i32 0, i32 0, i32 1, i32 0, i32 0, i32 0, i32 0)
|
|
%r0 = extractelement <4 x float> %r, i32 0
|
|
%r1 = extractelement <4 x float> %r, i32 1
|
|
%r2 = extractelement <4 x float> %r, i32 2
|
|
%r3 = extractelement <4 x float> %r, i32 3
|
|
call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %r0, float %r1, float %r2, float %r3)
|
|
ret void
|
|
}
|
|
|
|
;CHECK-LABEL: {{^}}gather4_c_cl_v8:
|
|
;CHECK: image_gather4_c_cl {{v\[[0-9]+:[0-9]+\]}}, 1, 0, 0, -1, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}
|
|
define void @gather4_c_cl_v8() #0 {
|
|
main_body:
|
|
%r = call <4 x float> @llvm.SI.gather4.c.cl.v8i32(<8 x i32> undef, <32 x i8> undef, <16 x i8> undef, i32 1, i32 0, i32 0, i32 1, i32 0, i32 0, i32 0, i32 0)
|
|
%r0 = extractelement <4 x float> %r, i32 0
|
|
%r1 = extractelement <4 x float> %r, i32 1
|
|
%r2 = extractelement <4 x float> %r, i32 2
|
|
%r3 = extractelement <4 x float> %r, i32 3
|
|
call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %r0, float %r1, float %r2, float %r3)
|
|
ret void
|
|
}
|
|
|
|
;CHECK-LABEL: {{^}}gather4_c_l:
|
|
;CHECK: image_gather4_c_l {{v\[[0-9]+:[0-9]+\]}}, 1, 0, 0, -1, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}
|
|
define void @gather4_c_l() #0 {
|
|
main_body:
|
|
%r = call <4 x float> @llvm.SI.gather4.c.l.v4i32(<4 x i32> undef, <32 x i8> undef, <16 x i8> undef, i32 1, i32 0, i32 0, i32 1, i32 0, i32 0, i32 0, i32 0)
|
|
%r0 = extractelement <4 x float> %r, i32 0
|
|
%r1 = extractelement <4 x float> %r, i32 1
|
|
%r2 = extractelement <4 x float> %r, i32 2
|
|
%r3 = extractelement <4 x float> %r, i32 3
|
|
call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %r0, float %r1, float %r2, float %r3)
|
|
ret void
|
|
}
|
|
|
|
;CHECK-LABEL: {{^}}gather4_c_l_v8:
|
|
;CHECK: image_gather4_c_l {{v\[[0-9]+:[0-9]+\]}}, 1, 0, 0, -1, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}
|
|
define void @gather4_c_l_v8() #0 {
|
|
main_body:
|
|
%r = call <4 x float> @llvm.SI.gather4.c.l.v8i32(<8 x i32> undef, <32 x i8> undef, <16 x i8> undef, i32 1, i32 0, i32 0, i32 1, i32 0, i32 0, i32 0, i32 0)
|
|
%r0 = extractelement <4 x float> %r, i32 0
|
|
%r1 = extractelement <4 x float> %r, i32 1
|
|
%r2 = extractelement <4 x float> %r, i32 2
|
|
%r3 = extractelement <4 x float> %r, i32 3
|
|
call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %r0, float %r1, float %r2, float %r3)
|
|
ret void
|
|
}
|
|
|
|
;CHECK-LABEL: {{^}}gather4_c_b:
|
|
;CHECK: image_gather4_c_b {{v\[[0-9]+:[0-9]+\]}}, 1, 0, 0, -1, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}
|
|
define void @gather4_c_b() #0 {
|
|
main_body:
|
|
%r = call <4 x float> @llvm.SI.gather4.c.b.v4i32(<4 x i32> undef, <32 x i8> undef, <16 x i8> undef, i32 1, i32 0, i32 0, i32 1, i32 0, i32 0, i32 0, i32 0)
|
|
%r0 = extractelement <4 x float> %r, i32 0
|
|
%r1 = extractelement <4 x float> %r, i32 1
|
|
%r2 = extractelement <4 x float> %r, i32 2
|
|
%r3 = extractelement <4 x float> %r, i32 3
|
|
call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %r0, float %r1, float %r2, float %r3)
|
|
ret void
|
|
}
|
|
|
|
;CHECK-LABEL: {{^}}gather4_c_b_v8:
|
|
;CHECK: image_gather4_c_b {{v\[[0-9]+:[0-9]+\]}}, 1, 0, 0, -1, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}
|
|
define void @gather4_c_b_v8() #0 {
|
|
main_body:
|
|
%r = call <4 x float> @llvm.SI.gather4.c.b.v8i32(<8 x i32> undef, <32 x i8> undef, <16 x i8> undef, i32 1, i32 0, i32 0, i32 1, i32 0, i32 0, i32 0, i32 0)
|
|
%r0 = extractelement <4 x float> %r, i32 0
|
|
%r1 = extractelement <4 x float> %r, i32 1
|
|
%r2 = extractelement <4 x float> %r, i32 2
|
|
%r3 = extractelement <4 x float> %r, i32 3
|
|
call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %r0, float %r1, float %r2, float %r3)
|
|
ret void
|
|
}
|
|
|
|
;CHECK-LABEL: {{^}}gather4_c_b_cl:
|
|
;CHECK: image_gather4_c_b_cl {{v\[[0-9]+:[0-9]+\]}}, 1, 0, 0, -1, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}
|
|
define void @gather4_c_b_cl() #0 {
|
|
main_body:
|
|
%r = call <4 x float> @llvm.SI.gather4.c.b.cl.v8i32(<8 x i32> undef, <32 x i8> undef, <16 x i8> undef, i32 1, i32 0, i32 0, i32 1, i32 0, i32 0, i32 0, i32 0)
|
|
%r0 = extractelement <4 x float> %r, i32 0
|
|
%r1 = extractelement <4 x float> %r, i32 1
|
|
%r2 = extractelement <4 x float> %r, i32 2
|
|
%r3 = extractelement <4 x float> %r, i32 3
|
|
call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %r0, float %r1, float %r2, float %r3)
|
|
ret void
|
|
}
|
|
|
|
;CHECK-LABEL: {{^}}gather4_c_lz:
|
|
;CHECK: image_gather4_c_lz {{v\[[0-9]+:[0-9]+\]}}, 1, 0, 0, -1, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}
|
|
define void @gather4_c_lz() #0 {
|
|
main_body:
|
|
%r = call <4 x float> @llvm.SI.gather4.c.lz.v4i32(<4 x i32> undef, <32 x i8> undef, <16 x i8> undef, i32 1, i32 0, i32 0, i32 1, i32 0, i32 0, i32 0, i32 0)
|
|
%r0 = extractelement <4 x float> %r, i32 0
|
|
%r1 = extractelement <4 x float> %r, i32 1
|
|
%r2 = extractelement <4 x float> %r, i32 2
|
|
%r3 = extractelement <4 x float> %r, i32 3
|
|
call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %r0, float %r1, float %r2, float %r3)
|
|
ret void
|
|
}
|
|
|
|
|
|
|
|
;CHECK-LABEL: {{^}}gather4_c_o:
|
|
;CHECK: image_gather4_c_o {{v\[[0-9]+:[0-9]+\]}}, 1, 0, 0, -1, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}
|
|
define void @gather4_c_o() #0 {
|
|
main_body:
|
|
%r = call <4 x float> @llvm.SI.gather4.c.o.v4i32(<4 x i32> undef, <32 x i8> undef, <16 x i8> undef, i32 1, i32 0, i32 0, i32 1, i32 0, i32 0, i32 0, i32 0)
|
|
%r0 = extractelement <4 x float> %r, i32 0
|
|
%r1 = extractelement <4 x float> %r, i32 1
|
|
%r2 = extractelement <4 x float> %r, i32 2
|
|
%r3 = extractelement <4 x float> %r, i32 3
|
|
call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %r0, float %r1, float %r2, float %r3)
|
|
ret void
|
|
}
|
|
|
|
;CHECK-LABEL: {{^}}gather4_c_o_v8:
|
|
;CHECK: image_gather4_c_o {{v\[[0-9]+:[0-9]+\]}}, 1, 0, 0, -1, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}
|
|
define void @gather4_c_o_v8() #0 {
|
|
main_body:
|
|
%r = call <4 x float> @llvm.SI.gather4.c.o.v8i32(<8 x i32> undef, <32 x i8> undef, <16 x i8> undef, i32 1, i32 0, i32 0, i32 1, i32 0, i32 0, i32 0, i32 0)
|
|
%r0 = extractelement <4 x float> %r, i32 0
|
|
%r1 = extractelement <4 x float> %r, i32 1
|
|
%r2 = extractelement <4 x float> %r, i32 2
|
|
%r3 = extractelement <4 x float> %r, i32 3
|
|
call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %r0, float %r1, float %r2, float %r3)
|
|
ret void
|
|
}
|
|
|
|
;CHECK-LABEL: {{^}}gather4_c_cl_o:
|
|
;CHECK: image_gather4_c_cl_o {{v\[[0-9]+:[0-9]+\]}}, 1, 0, 0, -1, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}
|
|
define void @gather4_c_cl_o() #0 {
|
|
main_body:
|
|
%r = call <4 x float> @llvm.SI.gather4.c.cl.o.v8i32(<8 x i32> undef, <32 x i8> undef, <16 x i8> undef, i32 1, i32 0, i32 0, i32 1, i32 0, i32 0, i32 0, i32 0)
|
|
%r0 = extractelement <4 x float> %r, i32 0
|
|
%r1 = extractelement <4 x float> %r, i32 1
|
|
%r2 = extractelement <4 x float> %r, i32 2
|
|
%r3 = extractelement <4 x float> %r, i32 3
|
|
call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %r0, float %r1, float %r2, float %r3)
|
|
ret void
|
|
}
|
|
|
|
;CHECK-LABEL: {{^}}gather4_c_l_o:
|
|
;CHECK: image_gather4_c_l_o {{v\[[0-9]+:[0-9]+\]}}, 1, 0, 0, -1, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}
|
|
define void @gather4_c_l_o() #0 {
|
|
main_body:
|
|
%r = call <4 x float> @llvm.SI.gather4.c.l.o.v8i32(<8 x i32> undef, <32 x i8> undef, <16 x i8> undef, i32 1, i32 0, i32 0, i32 1, i32 0, i32 0, i32 0, i32 0)
|
|
%r0 = extractelement <4 x float> %r, i32 0
|
|
%r1 = extractelement <4 x float> %r, i32 1
|
|
%r2 = extractelement <4 x float> %r, i32 2
|
|
%r3 = extractelement <4 x float> %r, i32 3
|
|
call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %r0, float %r1, float %r2, float %r3)
|
|
ret void
|
|
}
|
|
|
|
;CHECK-LABEL: {{^}}gather4_c_b_o:
|
|
;CHECK: image_gather4_c_b_o {{v\[[0-9]+:[0-9]+\]}}, 1, 0, 0, -1, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}
|
|
define void @gather4_c_b_o() #0 {
|
|
main_body:
|
|
%r = call <4 x float> @llvm.SI.gather4.c.b.o.v8i32(<8 x i32> undef, <32 x i8> undef, <16 x i8> undef, i32 1, i32 0, i32 0, i32 1, i32 0, i32 0, i32 0, i32 0)
|
|
%r0 = extractelement <4 x float> %r, i32 0
|
|
%r1 = extractelement <4 x float> %r, i32 1
|
|
%r2 = extractelement <4 x float> %r, i32 2
|
|
%r3 = extractelement <4 x float> %r, i32 3
|
|
call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %r0, float %r1, float %r2, float %r3)
|
|
ret void
|
|
}
|
|
|
|
;CHECK-LABEL: {{^}}gather4_c_b_cl_o:
|
|
;CHECK: image_gather4_c_b_cl_o {{v\[[0-9]+:[0-9]+\]}}, 1, 0, 0, -1, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}
|
|
define void @gather4_c_b_cl_o() #0 {
|
|
main_body:
|
|
%r = call <4 x float> @llvm.SI.gather4.c.b.cl.o.v8i32(<8 x i32> undef, <32 x i8> undef, <16 x i8> undef, i32 1, i32 0, i32 0, i32 1, i32 0, i32 0, i32 0, i32 0)
|
|
%r0 = extractelement <4 x float> %r, i32 0
|
|
%r1 = extractelement <4 x float> %r, i32 1
|
|
%r2 = extractelement <4 x float> %r, i32 2
|
|
%r3 = extractelement <4 x float> %r, i32 3
|
|
call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %r0, float %r1, float %r2, float %r3)
|
|
ret void
|
|
}
|
|
|
|
;CHECK-LABEL: {{^}}gather4_c_lz_o:
|
|
;CHECK: image_gather4_c_lz_o {{v\[[0-9]+:[0-9]+\]}}, 1, 0, 0, -1, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}
|
|
define void @gather4_c_lz_o() #0 {
|
|
main_body:
|
|
%r = call <4 x float> @llvm.SI.gather4.c.lz.o.v4i32(<4 x i32> undef, <32 x i8> undef, <16 x i8> undef, i32 1, i32 0, i32 0, i32 1, i32 0, i32 0, i32 0, i32 0)
|
|
%r0 = extractelement <4 x float> %r, i32 0
|
|
%r1 = extractelement <4 x float> %r, i32 1
|
|
%r2 = extractelement <4 x float> %r, i32 2
|
|
%r3 = extractelement <4 x float> %r, i32 3
|
|
call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %r0, float %r1, float %r2, float %r3)
|
|
ret void
|
|
}
|
|
|
|
;CHECK-LABEL: {{^}}gather4_c_lz_o_v8:
|
|
;CHECK: image_gather4_c_lz_o {{v\[[0-9]+:[0-9]+\]}}, 1, 0, 0, -1, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}
|
|
define void @gather4_c_lz_o_v8() #0 {
|
|
main_body:
|
|
%r = call <4 x float> @llvm.SI.gather4.c.lz.o.v8i32(<8 x i32> undef, <32 x i8> undef, <16 x i8> undef, i32 1, i32 0, i32 0, i32 1, i32 0, i32 0, i32 0, i32 0)
|
|
%r0 = extractelement <4 x float> %r, i32 0
|
|
%r1 = extractelement <4 x float> %r, i32 1
|
|
%r2 = extractelement <4 x float> %r, i32 2
|
|
%r3 = extractelement <4 x float> %r, i32 3
|
|
call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %r0, float %r1, float %r2, float %r3)
|
|
ret void
|
|
}
|
|
|
|
|
|
|
|
declare <4 x float> @llvm.SI.gather4.v2i32(<2 x i32>, <32 x i8>, <16 x i8>, i32, i32, i32, i32, i32, i32, i32, i32) #1
|
|
declare <4 x float> @llvm.SI.gather4.v4i32(<4 x i32>, <32 x i8>, <16 x i8>, i32, i32, i32, i32, i32, i32, i32, i32) #1
|
|
declare <4 x float> @llvm.SI.gather4.cl.v4i32(<4 x i32>, <32 x i8>, <16 x i8>, i32, i32, i32, i32, i32, i32, i32, i32) #1
|
|
declare <4 x float> @llvm.SI.gather4.l.v4i32(<4 x i32>, <32 x i8>, <16 x i8>, i32, i32, i32, i32, i32, i32, i32, i32) #1
|
|
declare <4 x float> @llvm.SI.gather4.b.v4i32(<4 x i32>, <32 x i8>, <16 x i8>, i32, i32, i32, i32, i32, i32, i32, i32) #1
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declare <4 x float> @llvm.SI.gather4.b.cl.v4i32(<4 x i32>, <32 x i8>, <16 x i8>, i32, i32, i32, i32, i32, i32, i32, i32) #1
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declare <4 x float> @llvm.SI.gather4.b.cl.v8i32(<8 x i32>, <32 x i8>, <16 x i8>, i32, i32, i32, i32, i32, i32, i32, i32) #1
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declare <4 x float> @llvm.SI.gather4.lz.v2i32(<2 x i32>, <32 x i8>, <16 x i8>, i32, i32, i32, i32, i32, i32, i32, i32) #1
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declare <4 x float> @llvm.SI.gather4.lz.v4i32(<4 x i32>, <32 x i8>, <16 x i8>, i32, i32, i32, i32, i32, i32, i32, i32) #1
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declare <4 x float> @llvm.SI.gather4.o.v4i32(<4 x i32>, <32 x i8>, <16 x i8>, i32, i32, i32, i32, i32, i32, i32, i32) #1
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declare <4 x float> @llvm.SI.gather4.cl.o.v4i32(<4 x i32>, <32 x i8>, <16 x i8>, i32, i32, i32, i32, i32, i32, i32, i32) #1
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declare <4 x float> @llvm.SI.gather4.cl.o.v8i32(<8 x i32>, <32 x i8>, <16 x i8>, i32, i32, i32, i32, i32, i32, i32, i32) #1
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declare <4 x float> @llvm.SI.gather4.l.o.v4i32(<4 x i32>, <32 x i8>, <16 x i8>, i32, i32, i32, i32, i32, i32, i32, i32) #1
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declare <4 x float> @llvm.SI.gather4.l.o.v8i32(<8 x i32>, <32 x i8>, <16 x i8>, i32, i32, i32, i32, i32, i32, i32, i32) #1
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declare <4 x float> @llvm.SI.gather4.b.o.v4i32(<4 x i32>, <32 x i8>, <16 x i8>, i32, i32, i32, i32, i32, i32, i32, i32) #1
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declare <4 x float> @llvm.SI.gather4.b.o.v8i32(<8 x i32>, <32 x i8>, <16 x i8>, i32, i32, i32, i32, i32, i32, i32, i32) #1
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declare <4 x float> @llvm.SI.gather4.b.cl.o.v8i32(<8 x i32>, <32 x i8>, <16 x i8>, i32, i32, i32, i32, i32, i32, i32, i32) #1
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declare <4 x float> @llvm.SI.gather4.lz.o.v4i32(<4 x i32>, <32 x i8>, <16 x i8>, i32, i32, i32, i32, i32, i32, i32, i32) #1
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declare <4 x float> @llvm.SI.gather4.c.v4i32(<4 x i32>, <32 x i8>, <16 x i8>, i32, i32, i32, i32, i32, i32, i32, i32) #1
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declare <4 x float> @llvm.SI.gather4.c.cl.v4i32(<4 x i32>, <32 x i8>, <16 x i8>, i32, i32, i32, i32, i32, i32, i32, i32) #1
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declare <4 x float> @llvm.SI.gather4.c.cl.v8i32(<8 x i32>, <32 x i8>, <16 x i8>, i32, i32, i32, i32, i32, i32, i32, i32) #1
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declare <4 x float> @llvm.SI.gather4.c.l.v4i32(<4 x i32>, <32 x i8>, <16 x i8>, i32, i32, i32, i32, i32, i32, i32, i32) #1
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declare <4 x float> @llvm.SI.gather4.c.l.v8i32(<8 x i32>, <32 x i8>, <16 x i8>, i32, i32, i32, i32, i32, i32, i32, i32) #1
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declare <4 x float> @llvm.SI.gather4.c.b.v4i32(<4 x i32>, <32 x i8>, <16 x i8>, i32, i32, i32, i32, i32, i32, i32, i32) #1
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declare <4 x float> @llvm.SI.gather4.c.b.v8i32(<8 x i32>, <32 x i8>, <16 x i8>, i32, i32, i32, i32, i32, i32, i32, i32) #1
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declare <4 x float> @llvm.SI.gather4.c.b.cl.v8i32(<8 x i32>, <32 x i8>, <16 x i8>, i32, i32, i32, i32, i32, i32, i32, i32) #1
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declare <4 x float> @llvm.SI.gather4.c.lz.v4i32(<4 x i32>, <32 x i8>, <16 x i8>, i32, i32, i32, i32, i32, i32, i32, i32) #1
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declare <4 x float> @llvm.SI.gather4.c.o.v4i32(<4 x i32>, <32 x i8>, <16 x i8>, i32, i32, i32, i32, i32, i32, i32, i32) #1
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declare <4 x float> @llvm.SI.gather4.c.o.v8i32(<8 x i32>, <32 x i8>, <16 x i8>, i32, i32, i32, i32, i32, i32, i32, i32) #1
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declare <4 x float> @llvm.SI.gather4.c.cl.o.v8i32(<8 x i32>, <32 x i8>, <16 x i8>, i32, i32, i32, i32, i32, i32, i32, i32) #1
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declare <4 x float> @llvm.SI.gather4.c.l.o.v8i32(<8 x i32>, <32 x i8>, <16 x i8>, i32, i32, i32, i32, i32, i32, i32, i32) #1
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declare <4 x float> @llvm.SI.gather4.c.b.o.v8i32(<8 x i32>, <32 x i8>, <16 x i8>, i32, i32, i32, i32, i32, i32, i32, i32) #1
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declare <4 x float> @llvm.SI.gather4.c.b.cl.o.v8i32(<8 x i32>, <32 x i8>, <16 x i8>, i32, i32, i32, i32, i32, i32, i32, i32) #1
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declare <4 x float> @llvm.SI.gather4.c.lz.o.v4i32(<4 x i32>, <32 x i8>, <16 x i8>, i32, i32, i32, i32, i32, i32, i32, i32) #1
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declare <4 x float> @llvm.SI.gather4.c.lz.o.v8i32(<8 x i32>, <32 x i8>, <16 x i8>, i32, i32, i32, i32, i32, i32, i32, i32) #1
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declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
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attributes #0 = { "ShaderType"="0" }
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attributes #1 = { nounwind readnone }
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