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808d878a96
llvm-6502/test/CodeGen
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Bill Schmidt 808d878a96 [PPC64] Fix PR20071 (fctiduz generated for targets lacking that instruction) 
PR20071 identifies a problem in PowerPC's fast-isel implementation for
floating-point conversion to integer.  The fctiduz instruction was added in
Power ISA 2.06 (i.e., Power7 and later).  However, this instruction is being
generated regardless of which 64-bit PowerPC target is selected.

The intent is for fast-isel to punt to DAG selection when this instruction is
not available.  This patch implements that change.  For testing purposes, the
existing fast-isel-conversion.ll test adds a RUN line for -mcpu=970 and tests
for the expected code generation.  Additionally, the existing test
fast-isel-conversion-p5.ll was found to be incorrectly expecting the
unavailable instruction to be generated.  I've removed these test variants
since we have adequate coverage in fast-isel-conversion.ll.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211627 91177308-0d34-0410-b5e6-96231b3b80d8
2014-06-24 20:05:18 +00:00
..
AArch64 Resubmit commit r211533 2014-06-24 16:21:38 +00:00
ARM ARMEB: Vector extend operations 2014-06-23 18:05:53 +00:00
CPP IR: add "cmpxchg weak" variant to support permitted failure. 2014-06-13 14:24:07 +00:00
Generic
Hexagon
Inputs
Mips [Mips] Add a target streamer when creating a null streamer. 2014-06-23 19:43:40 +00:00
MSP430
NVPTX Canonicalize addrspacecast ConstExpr between different pointer types 2014-06-15 21:40:57 +00:00
PowerPC [PPC64] Fix PR20071 (fctiduz generated for targets lacking that instruction) 2014-06-24 20:05:18 +00:00
R600 R600/SI: Fix div_scale intrinsic. 2014-06-23 18:28:28 +00:00
SPARC IR: add "cmpxchg weak" variant to support permitted failure. 2014-06-13 14:24:07 +00:00
SystemZ IR: add "cmpxchg weak" variant to support permitted failure. 2014-06-13 14:24:07 +00:00
Thumb ARM: Fix fastcc calling convention for Thumb1 2014-06-13 08:33:03 +00:00
Thumb2 ARM: Fix TPsoft for Thumb mode 2014-06-24 15:45:59 +00:00
X86 vpblend intrinsics combines as shifts intrinsics due to absence return stmt between them 2014-06-24 18:08:04 +00:00
XCore