Karthik Bhat d2ce9392dc Add Support to Recognize and Vectorize NON SIMD instructions in SLPVectorizer. ... This patch adds support to recognize patterns such as fadd,fsub,fadd,fsub.../add,sub,add,sub... and vectorizes them as vector shuffles if they are profitable. These patterns of vector shuffle can later be converted to instructions such as addsubpd etc on X86. Thanks to Arnold and Hal for the reviews. http://reviews.llvm.org/D4015 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211339 91177308-0d34-0410-b5e6-96231b3b80d8		2014-06-20 04:32:48 +00:00
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AArch64
ARM
R600
X86	Add Support to Recognize and Vectorize NON SIMD instructions in SLPVectorizer.	2014-06-20 04:32:48 +00:00
XCore