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30eae3c022
When compiling in Thumb mode, only the low (R0-R7) registers are available for most instructions. Breaking the low registers into a new register class handles this. Uses of R12, SP, etc, are handled explicitly where needed with copies inserted to move results into low registers where the rest of the code generator can deal with them. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@68545 91177308-0d34-0410-b5e6-96231b3b80d8
103 lines
3.5 KiB
C++
103 lines
3.5 KiB
C++
//===- ARMRegisterInfo.h - ARM Register Information Impl --------*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains the ARM implementation of the TargetRegisterInfo class.
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//
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//===----------------------------------------------------------------------===//
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#ifndef ARMREGISTERINFO_H
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#define ARMREGISTERINFO_H
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#include "llvm/Target/TargetRegisterInfo.h"
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#include "ARMGenRegisterInfo.h.inc"
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namespace llvm {
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class ARMSubtarget;
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class TargetInstrInfo;
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class Type;
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struct ARMRegisterInfo : public ARMGenRegisterInfo {
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const TargetInstrInfo &TII;
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const ARMSubtarget &STI;
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private:
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/// FramePtr - ARM physical register used as frame ptr.
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unsigned FramePtr;
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public:
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ARMRegisterInfo(const TargetInstrInfo &tii, const ARMSubtarget &STI);
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/// emitLoadConstPool - Emits a load from constpool to materialize the
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/// specified immediate.
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void emitLoadConstPool(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator &MBBI,
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unsigned DestReg, int Val,
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unsigned Pred, unsigned PredReg,
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const TargetInstrInfo *TII, bool isThumb,
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DebugLoc dl) const;
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/// getRegisterNumbering - Given the enum value for some register, e.g.
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/// ARM::LR, return the number that it corresponds to (e.g. 14).
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static unsigned getRegisterNumbering(unsigned RegEnum);
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/// Same as previous getRegisterNumbering except it returns true in isSPVFP
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/// if the register is a single precision VFP register.
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static unsigned getRegisterNumbering(unsigned RegEnum, bool &isSPVFP);
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/// getPointerRegClass - Return the register class to use to hold pointers.
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/// This is used for addressing modes.
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const TargetRegisterClass *getPointerRegClass() const;
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/// Code Generation virtual methods...
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const TargetRegisterClass *
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getPhysicalRegisterRegClass(unsigned Reg, MVT VT = MVT::Other) const;
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const unsigned *getCalleeSavedRegs(const MachineFunction *MF = 0) const;
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const TargetRegisterClass* const*
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getCalleeSavedRegClasses(const MachineFunction *MF = 0) const;
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BitVector getReservedRegs(const MachineFunction &MF) const;
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bool isReservedReg(const MachineFunction &MF, unsigned Reg) const;
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bool requiresRegisterScavenging(const MachineFunction &MF) const;
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bool hasFP(const MachineFunction &MF) const;
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bool hasReservedCallFrame(MachineFunction &MF) const;
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void eliminateCallFramePseudoInstr(MachineFunction &MF,
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MachineBasicBlock &MBB,
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MachineBasicBlock::iterator I) const;
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void eliminateFrameIndex(MachineBasicBlock::iterator II,
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int SPAdj, RegScavenger *RS = NULL) const;
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void processFunctionBeforeCalleeSavedScan(MachineFunction &MF,
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RegScavenger *RS = NULL) const;
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void emitPrologue(MachineFunction &MF) const;
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void emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const;
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// Debug information queries.
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unsigned getRARegister() const;
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unsigned getFrameRegister(MachineFunction &MF) const;
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// Exception handling queries.
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unsigned getEHExceptionRegister() const;
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unsigned getEHHandlerRegister() const;
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int getDwarfRegNum(unsigned RegNum, bool isEH) const;
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bool isLowRegister(unsigned Reg) const;
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};
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} // end namespace llvm
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#endif
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