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https://github.com/c64scene-ar/llvm-6502.git
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3f5d63b956
Reviewed-by: Vincent Lejeune <vljn at ovi.com> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186922 91177308-0d34-0410-b5e6-96231b3b80d8
386 lines
12 KiB
TableGen
386 lines
12 KiB
TableGen
//===-- AMDGPUInstructions.td - Common instruction defs ---*- tablegen -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains instruction defs that are common to all hw codegen
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// targets.
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//
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//===----------------------------------------------------------------------===//
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class AMDGPUInst <dag outs, dag ins, string asm, list<dag> pattern> : Instruction {
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field bit isRegisterLoad = 0;
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field bit isRegisterStore = 0;
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let Namespace = "AMDGPU";
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let OutOperandList = outs;
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let InOperandList = ins;
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let AsmString = asm;
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let Pattern = pattern;
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let Itinerary = NullALU;
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let TSFlags{63} = isRegisterLoad;
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let TSFlags{62} = isRegisterStore;
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}
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class AMDGPUShaderInst <dag outs, dag ins, string asm, list<dag> pattern>
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: AMDGPUInst<outs, ins, asm, pattern> {
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field bits<32> Inst = 0xffffffff;
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}
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def InstFlag : OperandWithDefaultOps <i32, (ops (i32 0))>;
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def COND_EQ : PatLeaf <
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(cond),
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[{switch(N->get()){{default: return false;
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case ISD::SETOEQ: case ISD::SETUEQ:
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case ISD::SETEQ: return true;}}}]
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>;
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def COND_NE : PatLeaf <
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(cond),
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[{switch(N->get()){{default: return false;
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case ISD::SETONE: case ISD::SETUNE:
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case ISD::SETNE: return true;}}}]
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>;
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def COND_GT : PatLeaf <
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(cond),
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[{switch(N->get()){{default: return false;
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case ISD::SETOGT: case ISD::SETUGT:
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case ISD::SETGT: return true;}}}]
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>;
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def COND_GE : PatLeaf <
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(cond),
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[{switch(N->get()){{default: return false;
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case ISD::SETOGE: case ISD::SETUGE:
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case ISD::SETGE: return true;}}}]
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>;
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def COND_LT : PatLeaf <
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(cond),
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[{switch(N->get()){{default: return false;
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case ISD::SETOLT: case ISD::SETULT:
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case ISD::SETLT: return true;}}}]
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>;
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def COND_LE : PatLeaf <
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(cond),
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[{switch(N->get()){{default: return false;
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case ISD::SETOLE: case ISD::SETULE:
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case ISD::SETLE: return true;}}}]
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>;
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def COND_NULL : PatLeaf <
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(cond),
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[{return false;}]
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>;
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//===----------------------------------------------------------------------===//
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// Load/Store Pattern Fragments
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//===----------------------------------------------------------------------===//
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def az_extload : PatFrag<(ops node:$ptr), (unindexedload node:$ptr), [{
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LoadSDNode *L = cast<LoadSDNode>(N);
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return L->getExtensionType() == ISD::ZEXTLOAD ||
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L->getExtensionType() == ISD::EXTLOAD;
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}]>;
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def az_extloadi8 : PatFrag<(ops node:$ptr), (az_extload node:$ptr), [{
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return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i8;
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}]>;
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def sextloadi8_global : PatFrag<(ops node:$ptr), (sextloadi8 node:$ptr), [{
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return isGlobalLoad(dyn_cast<LoadSDNode>(N));
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}]>;
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def az_extloadi8_constant : PatFrag<(ops node:$ptr), (az_extloadi8 node:$ptr), [{
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return isConstantLoad(dyn_cast<LoadSDNode>(N), -1);
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}]>;
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def sextloadi8_constant : PatFrag<(ops node:$ptr), (sextloadi8 node:$ptr), [{
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return isConstantLoad(dyn_cast<LoadSDNode>(N), -1);
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}]>;
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def az_extloadi8_global : PatFrag<(ops node:$ptr), (az_extloadi8 node:$ptr), [{
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return isGlobalLoad(dyn_cast<LoadSDNode>(N));
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}]>;
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def az_extloadi16 : PatFrag<(ops node:$ptr), (az_extload node:$ptr), [{
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return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i16;
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}]>;
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def az_extloadi16_global : PatFrag<(ops node:$ptr), (az_extloadi16 node:$ptr), [{
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return isGlobalLoad(dyn_cast<LoadSDNode>(N));
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}]>;
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def sextloadi16_global : PatFrag<(ops node:$ptr), (sextloadi16 node:$ptr), [{
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return isGlobalLoad(dyn_cast<LoadSDNode>(N));
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}]>;
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def az_extloadi16_constant : PatFrag<(ops node:$ptr), (az_extloadi16 node:$ptr), [{
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return isConstantLoad(dyn_cast<LoadSDNode>(N), -1);
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}]>;
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def sextloadi16_constant : PatFrag<(ops node:$ptr), (sextloadi16 node:$ptr), [{
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return isConstantLoad(dyn_cast<LoadSDNode>(N), -1);
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}]>;
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def az_extloadi32 : PatFrag<(ops node:$ptr), (az_extload node:$ptr), [{
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return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i32;
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}]>;
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def az_extloadi32_global : PatFrag<(ops node:$ptr),
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(az_extloadi32 node:$ptr), [{
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return isGlobalLoad(dyn_cast<LoadSDNode>(N));
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}]>;
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def az_extloadi32_constant : PatFrag<(ops node:$ptr),
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(az_extloadi32 node:$ptr), [{
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return isConstantLoad(dyn_cast<LoadSDNode>(N), -1);
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}]>;
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def local_load : PatFrag<(ops node:$ptr), (load node:$ptr), [{
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return isLocalLoad(dyn_cast<LoadSDNode>(N));
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}]>;
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def local_store : PatFrag<(ops node:$val, node:$ptr),
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(store node:$val, node:$ptr), [{
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return isLocalStore(dyn_cast<StoreSDNode>(N));
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}]>;
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class Constants {
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int TWO_PI = 0x40c90fdb;
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int PI = 0x40490fdb;
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int TWO_PI_INV = 0x3e22f983;
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int FP_UINT_MAX_PLUS_1 = 0x4f800000; // 1 << 32 in floating point encoding
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}
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def CONST : Constants;
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def FP_ZERO : PatLeaf <
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(fpimm),
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[{return N->getValueAPF().isZero();}]
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>;
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def FP_ONE : PatLeaf <
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(fpimm),
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[{return N->isExactlyValue(1.0);}]
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>;
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def U24 : ComplexPattern<i32, 1, "SelectU24", [], []>;
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def I24 : ComplexPattern<i32, 1, "SelectI24", [], []>;
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let isCodeGenOnly = 1, isPseudo = 1 in {
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let usesCustomInserter = 1 in {
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class CLAMP <RegisterClass rc> : AMDGPUShaderInst <
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(outs rc:$dst),
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(ins rc:$src0),
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"CLAMP $dst, $src0",
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[(set f32:$dst, (int_AMDIL_clamp f32:$src0, (f32 FP_ZERO), (f32 FP_ONE)))]
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>;
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class FABS <RegisterClass rc> : AMDGPUShaderInst <
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(outs rc:$dst),
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(ins rc:$src0),
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"FABS $dst, $src0",
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[(set f32:$dst, (fabs f32:$src0))]
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>;
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class FNEG <RegisterClass rc> : AMDGPUShaderInst <
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(outs rc:$dst),
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(ins rc:$src0),
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"FNEG $dst, $src0",
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[(set f32:$dst, (fneg f32:$src0))]
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>;
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} // usesCustomInserter = 1
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multiclass RegisterLoadStore <RegisterClass dstClass, Operand addrClass,
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ComplexPattern addrPat> {
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def RegisterLoad : AMDGPUShaderInst <
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(outs dstClass:$dst),
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(ins addrClass:$addr, i32imm:$chan),
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"RegisterLoad $dst, $addr",
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[(set i32:$dst, (AMDGPUregister_load addrPat:$addr, (i32 timm:$chan)))]
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> {
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let isRegisterLoad = 1;
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}
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def RegisterStore : AMDGPUShaderInst <
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(outs),
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(ins dstClass:$val, addrClass:$addr, i32imm:$chan),
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"RegisterStore $val, $addr",
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[(AMDGPUregister_store i32:$val, addrPat:$addr, (i32 timm:$chan))]
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> {
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let isRegisterStore = 1;
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}
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}
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} // End isCodeGenOnly = 1, isPseudo = 1
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/* Generic helper patterns for intrinsics */
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/* -------------------------------------- */
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class POW_Common <AMDGPUInst log_ieee, AMDGPUInst exp_ieee, AMDGPUInst mul>
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: Pat <
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(fpow f32:$src0, f32:$src1),
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(exp_ieee (mul f32:$src1, (log_ieee f32:$src0)))
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>;
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/* Other helper patterns */
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/* --------------------- */
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/* Extract element pattern */
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class Extract_Element <ValueType sub_type, ValueType vec_type, int sub_idx,
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SubRegIndex sub_reg>
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: Pat<
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(sub_type (vector_extract vec_type:$src, sub_idx)),
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(EXTRACT_SUBREG $src, sub_reg)
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>;
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/* Insert element pattern */
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class Insert_Element <ValueType elem_type, ValueType vec_type,
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int sub_idx, SubRegIndex sub_reg>
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: Pat <
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(vector_insert vec_type:$vec, elem_type:$elem, sub_idx),
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(INSERT_SUBREG $vec, $elem, sub_reg)
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>;
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// Vector Build pattern
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class Vector1_Build <ValueType vecType, ValueType elemType,
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RegisterClass rc> : Pat <
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(vecType (build_vector elemType:$src)),
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(vecType (COPY_TO_REGCLASS $src, rc))
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>;
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class Vector2_Build <ValueType vecType, ValueType elemType> : Pat <
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(vecType (build_vector elemType:$sub0, elemType:$sub1)),
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(INSERT_SUBREG (INSERT_SUBREG
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(vecType (IMPLICIT_DEF)), $sub0, sub0), $sub1, sub1)
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>;
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class Vector4_Build <ValueType vecType, ValueType elemType> : Pat <
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(vecType (build_vector elemType:$x, elemType:$y, elemType:$z, elemType:$w)),
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(INSERT_SUBREG (INSERT_SUBREG (INSERT_SUBREG (INSERT_SUBREG
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(vecType (IMPLICIT_DEF)), $x, sub0), $y, sub1), $z, sub2), $w, sub3)
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>;
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class Vector8_Build <ValueType vecType, ValueType elemType> : Pat <
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(vecType (build_vector elemType:$sub0, elemType:$sub1,
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elemType:$sub2, elemType:$sub3,
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elemType:$sub4, elemType:$sub5,
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elemType:$sub6, elemType:$sub7)),
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(INSERT_SUBREG (INSERT_SUBREG (INSERT_SUBREG (INSERT_SUBREG
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(INSERT_SUBREG (INSERT_SUBREG (INSERT_SUBREG (INSERT_SUBREG
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(vecType (IMPLICIT_DEF)), $sub0, sub0), $sub1, sub1),
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$sub2, sub2), $sub3, sub3),
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$sub4, sub4), $sub5, sub5),
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$sub6, sub6), $sub7, sub7)
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>;
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class Vector16_Build <ValueType vecType, ValueType elemType> : Pat <
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(vecType (build_vector elemType:$sub0, elemType:$sub1,
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elemType:$sub2, elemType:$sub3,
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elemType:$sub4, elemType:$sub5,
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elemType:$sub6, elemType:$sub7,
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elemType:$sub8, elemType:$sub9,
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elemType:$sub10, elemType:$sub11,
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elemType:$sub12, elemType:$sub13,
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elemType:$sub14, elemType:$sub15)),
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(INSERT_SUBREG (INSERT_SUBREG (INSERT_SUBREG (INSERT_SUBREG
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(INSERT_SUBREG (INSERT_SUBREG (INSERT_SUBREG (INSERT_SUBREG
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(INSERT_SUBREG (INSERT_SUBREG (INSERT_SUBREG (INSERT_SUBREG
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(INSERT_SUBREG (INSERT_SUBREG (INSERT_SUBREG (INSERT_SUBREG
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(vecType (IMPLICIT_DEF)), $sub0, sub0), $sub1, sub1),
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$sub2, sub2), $sub3, sub3),
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$sub4, sub4), $sub5, sub5),
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$sub6, sub6), $sub7, sub7),
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$sub8, sub8), $sub9, sub9),
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$sub10, sub10), $sub11, sub11),
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$sub12, sub12), $sub13, sub13),
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$sub14, sub14), $sub15, sub15)
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>;
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// XXX: Convert to new syntax and use COPY_TO_REG, once the DFAPacketizer
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// can handle COPY instructions.
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// bitconvert pattern
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class BitConvert <ValueType dt, ValueType st, RegisterClass rc> : Pat <
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(dt (bitconvert (st rc:$src0))),
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(dt rc:$src0)
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>;
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// XXX: Convert to new syntax and use COPY_TO_REG, once the DFAPacketizer
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// can handle COPY instructions.
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class DwordAddrPat<ValueType vt, RegisterClass rc> : Pat <
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(vt (AMDGPUdwordaddr (vt rc:$addr))),
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(vt rc:$addr)
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>;
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// BFI_INT patterns
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multiclass BFIPatterns <Instruction BFI_INT> {
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// Definition from ISA doc:
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// (y & x) | (z & ~x)
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def : Pat <
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(or (and i32:$y, i32:$x), (and i32:$z, (not i32:$x))),
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(BFI_INT $x, $y, $z)
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>;
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// SHA-256 Ch function
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// z ^ (x & (y ^ z))
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def : Pat <
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(xor i32:$z, (and i32:$x, (xor i32:$y, i32:$z))),
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(BFI_INT $x, $y, $z)
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>;
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}
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// SHA-256 Ma patterns
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// ((x & z) | (y & (x | z))) -> BFI_INT (XOR x, y), z, y
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class SHA256MaPattern <Instruction BFI_INT, Instruction XOR> : Pat <
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(or (and i32:$x, i32:$z), (and i32:$y, (or i32:$x, i32:$z))),
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(BFI_INT (XOR i32:$x, i32:$y), i32:$z, i32:$y)
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>;
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// Bitfield extract patterns
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def legalshift32 : ImmLeaf <i32, [{return Imm >=0 && Imm < 32;}]>;
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def bfemask : PatLeaf <(imm), [{return isMask_32(N->getZExtValue());}],
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SDNodeXForm<imm, [{ return CurDAG->getTargetConstant(CountTrailingOnes_32(N->getZExtValue()), MVT::i32);}]>>;
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class BFEPattern <Instruction BFE> : Pat <
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(and (srl i32:$x, legalshift32:$y), bfemask:$z),
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(BFE $x, $y, $z)
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>;
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// rotr pattern
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class ROTRPattern <Instruction BIT_ALIGN> : Pat <
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(rotr i32:$src0, i32:$src1),
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(BIT_ALIGN $src0, $src0, $src1)
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>;
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// 24-bit arithmetic patterns
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def umul24 : PatFrag <(ops node:$x, node:$y), (mul node:$x, node:$y)>;
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/*
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class UMUL24Pattern <Instruction UMUL24> : Pat <
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(mul U24:$x, U24:$y),
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(UMUL24 $x, $y)
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>;
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*/
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include "R600Instructions.td"
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include "SIInstrInfo.td"
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