mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-11-05 13:09:10 +00:00
ec2aaad01b
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183589 91177308-0d34-0410-b5e6-96231b3b80d8
359 lines
14 KiB
TableGen
359 lines
14 KiB
TableGen
//===-- SparcInstr64Bit.td - 64-bit instructions for Sparc Target ---------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains instruction definitions and patterns needed for 64-bit
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// code generation on SPARC v9.
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//
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// Some SPARC v9 instructions are defined in SparcInstrInfo.td because they can
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// also be used in 32-bit code running on a SPARC v9 CPU.
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//
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//===----------------------------------------------------------------------===//
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let Predicates = [Is64Bit] in {
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// The same integer registers are used for i32 and i64 values.
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// When registers hold i32 values, the high bits are don't care.
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// This give us free trunc and anyext.
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def : Pat<(i64 (anyext i32:$val)), (COPY_TO_REGCLASS $val, I64Regs)>;
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def : Pat<(i32 (trunc i64:$val)), (COPY_TO_REGCLASS $val, IntRegs)>;
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} // Predicates = [Is64Bit]
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//===----------------------------------------------------------------------===//
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// 64-bit Shift Instructions.
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//===----------------------------------------------------------------------===//
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//
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// The 32-bit shift instructions are still available. The left shift srl
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// instructions shift all 64 bits, but it only accepts a 5-bit shift amount.
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//
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// The srl instructions only shift the low 32 bits and clear the high 32 bits.
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// Finally, sra shifts the low 32 bits and sign-extends to 64 bits.
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let Predicates = [Is64Bit] in {
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def : Pat<(i64 (zext i32:$val)), (SRLri $val, 0)>;
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def : Pat<(i64 (sext i32:$val)), (SRAri $val, 0)>;
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def : Pat<(i64 (and i64:$val, 0xffffffff)), (SRLri $val, 0)>;
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def : Pat<(i64 (sext_inreg i64:$val, i32)), (SRAri $val, 0)>;
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defm SLLX : F3_S<"sllx", 0b100101, 1, shl, i64, I64Regs>;
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defm SRLX : F3_S<"srlx", 0b100110, 1, srl, i64, I64Regs>;
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defm SRAX : F3_S<"srax", 0b100111, 1, sra, i64, I64Regs>;
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} // Predicates = [Is64Bit]
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//===----------------------------------------------------------------------===//
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// 64-bit Immediates.
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//===----------------------------------------------------------------------===//
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//
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// All 32-bit immediates can be materialized with sethi+or, but 64-bit
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// immediates may require more code. There may be a point where it is
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// preferable to use a constant pool load instead, depending on the
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// microarchitecture.
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// Single-instruction patterns.
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// The ALU instructions want their simm13 operands as i32 immediates.
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def as_i32imm : SDNodeXForm<imm, [{
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return CurDAG->getTargetConstant(N->getSExtValue(), MVT::i32);
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}]>;
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def : Pat<(i64 simm13:$val), (ORri (i64 G0), (as_i32imm $val))>;
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def : Pat<(i64 SETHIimm:$val), (SETHIi (HI22 $val))>;
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// Double-instruction patterns.
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// All unsigned i32 immediates can be handled by sethi+or.
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def uimm32 : PatLeaf<(imm), [{ return isUInt<32>(N->getZExtValue()); }]>;
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def : Pat<(i64 uimm32:$val), (ORri (SETHIi (HI22 $val)), (LO10 $val))>,
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Requires<[Is64Bit]>;
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// All negative i33 immediates can be handled by sethi+xor.
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def nimm33 : PatLeaf<(imm), [{
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int64_t Imm = N->getSExtValue();
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return Imm < 0 && isInt<33>(Imm);
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}]>;
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// Bits 10-31 inverted. Same as assembler's %hix.
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def HIX22 : SDNodeXForm<imm, [{
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uint64_t Val = (~N->getZExtValue() >> 10) & ((1u << 22) - 1);
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return CurDAG->getTargetConstant(Val, MVT::i32);
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}]>;
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// Bits 0-9 with ones in bits 10-31. Same as assembler's %lox.
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def LOX10 : SDNodeXForm<imm, [{
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return CurDAG->getTargetConstant(~(~N->getZExtValue() & 0x3ff), MVT::i32);
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}]>;
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def : Pat<(i64 nimm33:$val), (XORri (SETHIi (HIX22 $val)), (LOX10 $val))>,
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Requires<[Is64Bit]>;
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// More possible patterns:
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//
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// (sllx sethi, n)
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// (sllx simm13, n)
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//
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// 3 instrs:
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//
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// (xor (sllx sethi), simm13)
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// (sllx (xor sethi, simm13))
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//
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// 4 instrs:
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//
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// (or sethi, (sllx sethi))
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// (xnor sethi, (sllx sethi))
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//
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// 5 instrs:
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//
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// (or (sllx sethi), (or sethi, simm13))
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// (xnor (sllx sethi), (or sethi, simm13))
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// (or (sllx sethi), (sllx sethi))
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// (xnor (sllx sethi), (sllx sethi))
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//
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// Worst case is 6 instrs:
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//
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// (or (sllx (or sethi, simmm13)), (or sethi, simm13))
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// Bits 42-63, same as assembler's %hh.
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def HH22 : SDNodeXForm<imm, [{
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uint64_t Val = (N->getZExtValue() >> 42) & ((1u << 22) - 1);
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return CurDAG->getTargetConstant(Val, MVT::i32);
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}]>;
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// Bits 32-41, same as assembler's %hm.
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def HM10 : SDNodeXForm<imm, [{
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uint64_t Val = (N->getZExtValue() >> 32) & ((1u << 10) - 1);
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return CurDAG->getTargetConstant(Val, MVT::i32);
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}]>;
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def : Pat<(i64 imm:$val),
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(ORrr (SLLXri (ORri (SETHIi (HH22 $val)), (HM10 $val)), (i32 32)),
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(ORri (SETHIi (HI22 $val)), (LO10 $val)))>,
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Requires<[Is64Bit]>;
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//===----------------------------------------------------------------------===//
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// 64-bit Integer Arithmetic and Logic.
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//===----------------------------------------------------------------------===//
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let Predicates = [Is64Bit] in {
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// Register-register instructions.
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def : Pat<(and i64:$a, i64:$b), (ANDrr $a, $b)>;
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def : Pat<(or i64:$a, i64:$b), (ORrr $a, $b)>;
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def : Pat<(xor i64:$a, i64:$b), (XORrr $a, $b)>;
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def : Pat<(and i64:$a, (not i64:$b)), (ANDNrr $a, $b)>;
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def : Pat<(or i64:$a, (not i64:$b)), (ORNrr $a, $b)>;
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def : Pat<(xor i64:$a, (not i64:$b)), (XNORrr $a, $b)>;
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def : Pat<(add i64:$a, i64:$b), (ADDrr $a, $b)>;
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def : Pat<(sub i64:$a, i64:$b), (SUBrr $a, $b)>;
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// Add/sub with carry were renamed to addc/subc in SPARC v9.
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def : Pat<(adde i64:$a, i64:$b), (ADDXrr $a, $b)>;
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def : Pat<(sube i64:$a, i64:$b), (SUBXrr $a, $b)>;
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def : Pat<(addc i64:$a, i64:$b), (ADDCCrr $a, $b)>;
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def : Pat<(subc i64:$a, i64:$b), (SUBCCrr $a, $b)>;
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def : Pat<(SPcmpicc i64:$a, i64:$b), (CMPrr $a, $b)>;
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// Register-immediate instructions.
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def : Pat<(and i64:$a, (i64 simm13:$b)), (ANDri $a, (as_i32imm $b))>;
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def : Pat<(or i64:$a, (i64 simm13:$b)), (ORri $a, (as_i32imm $b))>;
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def : Pat<(xor i64:$a, (i64 simm13:$b)), (XORri $a, (as_i32imm $b))>;
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def : Pat<(add i64:$a, (i64 simm13:$b)), (ADDri $a, (as_i32imm $b))>;
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def : Pat<(sub i64:$a, (i64 simm13:$b)), (SUBri $a, (as_i32imm $b))>;
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def : Pat<(SPcmpicc i64:$a, (i64 simm13:$b)), (CMPri $a, (as_i32imm $b))>;
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} // Predicates = [Is64Bit]
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//===----------------------------------------------------------------------===//
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// 64-bit Integer Multiply and Divide.
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//===----------------------------------------------------------------------===//
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let Predicates = [Is64Bit] in {
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def MULXrr : F3_1<2, 0b001001,
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(outs I64Regs:$rd), (ins I64Regs:$rs1, I64Regs:$rs2),
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"mulx $rs1, $rs2, $rd",
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[(set i64:$rd, (mul i64:$rs1, i64:$rs2))]>;
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def MULXri : F3_2<2, 0b001001,
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(outs IntRegs:$rd), (ins IntRegs:$rs1, i64imm:$i),
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"mulx $rs1, $i, $rd",
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[(set i64:$rd, (mul i64:$rs1, (i64 simm13:$i)))]>;
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// Division can trap.
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let hasSideEffects = 1 in {
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def SDIVXrr : F3_1<2, 0b101101,
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(outs I64Regs:$rd), (ins I64Regs:$rs1, I64Regs:$rs2),
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"sdivx $rs1, $rs2, $rd",
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[(set i64:$rd, (sdiv i64:$rs1, i64:$rs2))]>;
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def SDIVXri : F3_2<2, 0b101101,
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(outs IntRegs:$rd), (ins IntRegs:$rs1, i64imm:$i),
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"sdivx $rs1, $i, $rd",
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[(set i64:$rd, (sdiv i64:$rs1, (i64 simm13:$i)))]>;
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def UDIVXrr : F3_1<2, 0b001101,
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(outs I64Regs:$rd), (ins I64Regs:$rs1, I64Regs:$rs2),
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"udivx $rs1, $rs2, $rd",
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[(set i64:$rd, (udiv i64:$rs1, i64:$rs2))]>;
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def UDIVXri : F3_2<2, 0b001101,
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(outs IntRegs:$rd), (ins IntRegs:$rs1, i64imm:$i),
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"udivx $rs1, $i, $rd",
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[(set i64:$rd, (udiv i64:$rs1, (i64 simm13:$i)))]>;
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} // hasSideEffects = 1
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} // Predicates = [Is64Bit]
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//===----------------------------------------------------------------------===//
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// 64-bit Loads and Stores.
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//===----------------------------------------------------------------------===//
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//
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// All the 32-bit loads and stores are available. The extending loads are sign
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// or zero-extending to 64 bits. The LDrr and LDri instructions load 32 bits
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// zero-extended to i64. Their mnemonic is lduw in SPARC v9 (Load Unsigned
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// Word).
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//
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// SPARC v9 adds 64-bit loads as well as a sign-extending ldsw i32 loads.
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let Predicates = [Is64Bit] in {
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// 64-bit loads.
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def LDXrr : F3_1<3, 0b001011,
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(outs I64Regs:$dst), (ins MEMrr:$addr),
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"ldx [$addr], $dst",
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[(set i64:$dst, (load ADDRrr:$addr))]>;
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def LDXri : F3_2<3, 0b001011,
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(outs I64Regs:$dst), (ins MEMri:$addr),
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"ldx [$addr], $dst",
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[(set i64:$dst, (load ADDRri:$addr))]>;
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// Extending loads to i64.
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def : Pat<(i64 (zextloadi1 ADDRrr:$addr)), (LDUBrr ADDRrr:$addr)>;
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def : Pat<(i64 (zextloadi1 ADDRri:$addr)), (LDUBri ADDRri:$addr)>;
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def : Pat<(i64 (extloadi1 ADDRrr:$addr)), (LDUBrr ADDRrr:$addr)>;
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def : Pat<(i64 (extloadi1 ADDRri:$addr)), (LDUBri ADDRri:$addr)>;
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def : Pat<(i64 (zextloadi8 ADDRrr:$addr)), (LDUBrr ADDRrr:$addr)>;
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def : Pat<(i64 (zextloadi8 ADDRri:$addr)), (LDUBri ADDRri:$addr)>;
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def : Pat<(i64 (extloadi8 ADDRrr:$addr)), (LDUBrr ADDRrr:$addr)>;
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def : Pat<(i64 (extloadi8 ADDRri:$addr)), (LDUBri ADDRri:$addr)>;
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def : Pat<(i64 (sextloadi8 ADDRrr:$addr)), (LDSBrr ADDRrr:$addr)>;
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def : Pat<(i64 (sextloadi8 ADDRri:$addr)), (LDSBri ADDRri:$addr)>;
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def : Pat<(i64 (zextloadi16 ADDRrr:$addr)), (LDUHrr ADDRrr:$addr)>;
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def : Pat<(i64 (zextloadi16 ADDRri:$addr)), (LDUHri ADDRri:$addr)>;
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def : Pat<(i64 (extloadi16 ADDRrr:$addr)), (LDUHrr ADDRrr:$addr)>;
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def : Pat<(i64 (extloadi16 ADDRri:$addr)), (LDUHri ADDRri:$addr)>;
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def : Pat<(i64 (sextloadi16 ADDRrr:$addr)), (LDSHrr ADDRrr:$addr)>;
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def : Pat<(i64 (sextloadi16 ADDRri:$addr)), (LDSHri ADDRri:$addr)>;
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def : Pat<(i64 (zextloadi32 ADDRrr:$addr)), (LDrr ADDRrr:$addr)>;
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def : Pat<(i64 (zextloadi32 ADDRri:$addr)), (LDri ADDRri:$addr)>;
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def : Pat<(i64 (extloadi32 ADDRrr:$addr)), (LDrr ADDRrr:$addr)>;
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def : Pat<(i64 (extloadi32 ADDRri:$addr)), (LDri ADDRri:$addr)>;
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// Sign-extending load of i32 into i64 is a new SPARC v9 instruction.
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def LDSWrr : F3_1<3, 0b001011,
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(outs I64Regs:$dst), (ins MEMrr:$addr),
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"ldsw [$addr], $dst",
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[(set i64:$dst, (sextloadi32 ADDRrr:$addr))]>;
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def LDSWri : F3_2<3, 0b001011,
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(outs I64Regs:$dst), (ins MEMri:$addr),
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"ldsw [$addr], $dst",
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[(set i64:$dst, (sextloadi32 ADDRri:$addr))]>;
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// 64-bit stores.
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def STXrr : F3_1<3, 0b001110,
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(outs), (ins MEMrr:$addr, I64Regs:$src),
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"stx $src, [$addr]",
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[(store i64:$src, ADDRrr:$addr)]>;
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def STXri : F3_2<3, 0b001110,
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(outs), (ins MEMri:$addr, I64Regs:$src),
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"stx $src, [$addr]",
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[(store i64:$src, ADDRri:$addr)]>;
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// Truncating stores from i64 are identical to the i32 stores.
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def : Pat<(truncstorei8 i64:$src, ADDRrr:$addr), (STBrr ADDRrr:$addr, $src)>;
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def : Pat<(truncstorei8 i64:$src, ADDRri:$addr), (STBri ADDRri:$addr, $src)>;
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def : Pat<(truncstorei16 i64:$src, ADDRrr:$addr), (STHrr ADDRrr:$addr, $src)>;
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def : Pat<(truncstorei16 i64:$src, ADDRri:$addr), (STHri ADDRri:$addr, $src)>;
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def : Pat<(truncstorei32 i64:$src, ADDRrr:$addr), (STrr ADDRrr:$addr, $src)>;
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def : Pat<(truncstorei32 i64:$src, ADDRri:$addr), (STri ADDRri:$addr, $src)>;
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// store 0, addr -> store %g0, addr
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def : Pat<(store (i64 0), ADDRrr:$dst), (STXrr ADDRrr:$dst, (i64 G0))>;
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def : Pat<(store (i64 0), ADDRri:$dst), (STXri ADDRri:$dst, (i64 G0))>;
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} // Predicates = [Is64Bit]
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//===----------------------------------------------------------------------===//
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// 64-bit Conditionals.
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//===----------------------------------------------------------------------===//
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//
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// Flag-setting instructions like subcc and addcc set both icc and xcc flags.
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// The icc flags correspond to the 32-bit result, and the xcc are for the
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// full 64-bit result.
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//
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// We reuse CMPICC SDNodes for compares, but use new BRXCC branch nodes for
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// 64-bit compares. See LowerBR_CC.
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let Predicates = [Is64Bit] in {
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let Uses = [ICC] in
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def BPXCC : BranchSP<0, (ins brtarget:$dst, CCOp:$cc),
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"b$cc %xcc, $dst",
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[(SPbrxcc bb:$dst, imm:$cc)]>;
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// Conditional moves on %xcc.
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let Uses = [ICC], Constraints = "$f = $rd" in {
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def MOVXCCrr : Pseudo<(outs IntRegs:$rd),
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(ins IntRegs:$rs2, IntRegs:$f, CCOp:$cond),
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"mov$cond %xcc, $rs2, $rd",
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[(set i32:$rd,
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(SPselectxcc i32:$rs2, i32:$f, imm:$cond))]>;
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def MOVXCCri : Pseudo<(outs IntRegs:$rd),
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(ins i32imm:$i, IntRegs:$f, CCOp:$cond),
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"mov$cond %xcc, $i, $rd",
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[(set i32:$rd,
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(SPselectxcc simm11:$i, i32:$f, imm:$cond))]>;
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def FMOVS_XCC : Pseudo<(outs FPRegs:$rd),
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(ins FPRegs:$rs2, FPRegs:$f, CCOp:$cond),
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"fmovs$cond %xcc, $rs2, $rd",
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[(set f32:$rd,
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(SPselectxcc f32:$rs2, f32:$f, imm:$cond))]>;
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def FMOVD_XCC : Pseudo<(outs DFPRegs:$rd),
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(ins DFPRegs:$rs2, DFPRegs:$f, CCOp:$cond),
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"fmovd$cond %xcc, $rs2, $rd",
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[(set f64:$rd,
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(SPselectxcc f64:$rs2, f64:$f, imm:$cond))]>;
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} // Uses, Constraints
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def : Pat<(SPselectxcc i64:$t, i64:$f, imm:$cond),
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(MOVXCCrr $t, $f, imm:$cond)>;
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def : Pat<(SPselectxcc (i64 simm11:$t), i64:$f, imm:$cond),
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(MOVXCCri (as_i32imm $t), $f, imm:$cond)>;
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def : Pat<(SPselecticc i64:$t, i64:$f, imm:$cond),
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(MOVICCrr $t, $f, imm:$cond)>;
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def : Pat<(SPselecticc (i64 simm11:$t), i64:$f, imm:$cond),
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(MOVICCri (as_i32imm $t), $f, imm:$cond)>;
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def : Pat<(SPselectfcc i64:$t, i64:$f, imm:$cond),
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(MOVFCCrr $t, $f, imm:$cond)>;
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def : Pat<(SPselectfcc (i64 simm11:$t), i64:$f, imm:$cond),
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(MOVFCCri (as_i32imm $t), $f, imm:$cond)>;
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} // Predicates = [Is64Bit]
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