mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-11-05 13:09:10 +00:00
eddfaad1ef
This first step just adds definitions for SLLK, SRLK and SRAK. The next patch will actually make use of them during codegen. insn-bad.s tests that some form of error is reported when using these instructions on z10. More work is needed to get the "instruction requires: distinct-ops" that we'd ideally like, so I've stubbed that part out for now. I'll come back and make it mandatory once the necessary changes are in. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186680 91177308-0d34-0410-b5e6-96231b3b80d8
73 lines
2.5 KiB
TableGen
73 lines
2.5 KiB
TableGen
//===-- SystemZ.td - Describe the SystemZ target machine -----*- tblgen -*-===//
|
|
//
|
|
// The LLVM Compiler Infrastructure
|
|
//
|
|
// This file is distributed under the University of Illinois Open Source
|
|
// License. See LICENSE.TXT for details.
|
|
//
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// Target-independent interfaces which we are implementing
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
include "llvm/Target/Target.td"
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// SystemZ supported processors and features
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
include "SystemZProcessors.td"
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// Register file description
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
include "SystemZRegisterInfo.td"
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// Calling convention description
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
include "SystemZCallingConv.td"
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// Instruction descriptions
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
include "SystemZOperators.td"
|
|
include "SystemZOperands.td"
|
|
include "SystemZPatterns.td"
|
|
include "SystemZInstrFormats.td"
|
|
include "SystemZInstrInfo.td"
|
|
include "SystemZInstrFP.td"
|
|
|
|
def SystemZInstrInfo : InstrInfo {}
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// Assembly parser
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
def SystemZAsmParser : AsmParser {
|
|
let ShouldEmitMatchRegisterName = 0;
|
|
}
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// Assembly writer
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
def SystemZAsmWriter : AsmWriter {
|
|
string AsmWriterClassName = "InstPrinter";
|
|
bit isMCAsmWriter = 1;
|
|
}
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// Top-level target declaration
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
def SystemZ : Target {
|
|
let InstructionSet = SystemZInstrInfo;
|
|
let AssemblyParsers = [SystemZAsmParser];
|
|
let AssemblyWriters = [SystemZAsmWriter];
|
|
}
|