Eric Christopher 5dc2251b4e Recommit r231324 with a fix to the ARM execution domain code ... to disable lane switching if we don't actually have the instruction set we want to switch to. Models the earlier check above the conditional for the pass. The testcase is one that triggered with the assert that's added as part of the fix, use it to avoid adding a new testcase as it highlights the same problem. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@231539 91177308-0d34-0410-b5e6-96231b3b80d8		2015-03-07 00:12:22 +00:00
..
Analysis	Do not restrict interleaved unrolling to small loops, depending on the target.	2015-03-06 23:12:04 +00:00
AsmParser
Bitcode
CodeGen	DAGCombiner: Canonicalize select(and/or,x,y) depending on target.	2015-03-06 19:49:10 +00:00
DebugInfo	DWARFFormValue: Add getAsSignedConstant method.	2015-03-04 22:07:41 +00:00
ExecutionEngine	Fold init() helpers into constructors. NFC.	2015-03-06 16:21:15 +00:00
Fuzzer
IR	[ConstantRange] Teach multiply to be cleverer about signed ranges.	2015-03-06 15:50:47 +00:00
IRReader
LineEditor
Linker	Remember to move a type to the correct set when setting the body.	2015-03-06 00:50:21 +00:00
LTO
MC	Use the generic Lfunc_begin label on ppc.	2015-03-05 18:55:50 +00:00
Object
Option
ProfileData
Support	Support: Improve performance of FileOutputBuffer on Windows	2015-03-06 06:07:32 +00:00
TableGen
Target	Recommit r231324 with a fix to the ARM execution domain code	2015-03-07 00:12:22 +00:00
Transforms	Do not restrict interleaved unrolling to small loops, depending on the target.	2015-03-06 23:12:04 +00:00
CMakeLists.txt
LLVMBuild.txt
Makefile