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promoting allocas to preferred alignments that exceed the natural alignment. This avoids some potentially expensive dynamic stack realignments. The natural stack alignment is set in target data strings via the "S<size>" option. Size is in bits and must be a multiple of 8. The natural stack alignment defaults to "unspecified" (represented by a zero value), and the "unspecified" value does not prevent any alignment promotions. Target maintainers that care about avoiding promotions should explicitly add the "S<size>" option to their target data strings. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141599 91177308-0d34-0410-b5e6-96231b3b80d8
161 lines
6.1 KiB
C++
161 lines
6.1 KiB
C++
//===-- ARMTargetMachine.cpp - Define TargetMachine for ARM ---------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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//
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//===----------------------------------------------------------------------===//
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#include "ARMTargetMachine.h"
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#include "ARMFrameLowering.h"
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#include "ARM.h"
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#include "llvm/PassManager.h"
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#include "llvm/CodeGen/Passes.h"
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#include "llvm/MC/MCAsmInfo.h"
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#include "llvm/Support/CommandLine.h"
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#include "llvm/Support/FormattedStream.h"
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#include "llvm/Support/TargetRegistry.h"
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#include "llvm/Target/TargetOptions.h"
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using namespace llvm;
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static cl::opt<bool>
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EnableGlobalMerge("global-merge", cl::Hidden,
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cl::desc("Enable global merge pass"),
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cl::init(true));
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extern "C" void LLVMInitializeARMTarget() {
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// Register the target.
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RegisterTargetMachine<ARMTargetMachine> X(TheARMTarget);
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RegisterTargetMachine<ThumbTargetMachine> Y(TheThumbTarget);
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}
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/// TargetMachine ctor - Create an ARM architecture model.
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///
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ARMBaseTargetMachine::ARMBaseTargetMachine(const Target &T, StringRef TT,
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StringRef CPU, StringRef FS,
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Reloc::Model RM, CodeModel::Model CM)
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: LLVMTargetMachine(T, TT, CPU, FS, RM, CM),
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Subtarget(TT, CPU, FS),
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JITInfo(),
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InstrItins(Subtarget.getInstrItineraryData()) {
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// Default to soft float ABI
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if (FloatABIType == FloatABI::Default)
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FloatABIType = FloatABI::Soft;
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}
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ARMTargetMachine::ARMTargetMachine(const Target &T, StringRef TT,
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StringRef CPU, StringRef FS,
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Reloc::Model RM, CodeModel::Model CM)
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: ARMBaseTargetMachine(T, TT, CPU, FS, RM, CM), InstrInfo(Subtarget),
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DataLayout(Subtarget.isAPCS_ABI() ?
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std::string("e-p:32:32-f64:32:64-i64:32:64-"
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"v128:32:128-v64:32:64-n32-S32") :
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Subtarget.isAAPCS_ABI() ?
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std::string("e-p:32:32-f64:64:64-i64:64:64-"
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"v128:64:128-v64:64:64-n32-S64") :
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std::string("e-p:32:32-f64:64:64-i64:64:64-"
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"v128:64:128-v64:64:64-n32-S32")),
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ELFWriterInfo(*this),
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TLInfo(*this),
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TSInfo(*this),
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FrameLowering(Subtarget) {
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if (!Subtarget.hasARMOps())
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report_fatal_error("CPU: '" + Subtarget.getCPUString() + "' does not "
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"support ARM mode execution!");
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}
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ThumbTargetMachine::ThumbTargetMachine(const Target &T, StringRef TT,
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StringRef CPU, StringRef FS,
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Reloc::Model RM, CodeModel::Model CM)
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: ARMBaseTargetMachine(T, TT, CPU, FS, RM, CM),
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InstrInfo(Subtarget.hasThumb2()
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? ((ARMBaseInstrInfo*)new Thumb2InstrInfo(Subtarget))
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: ((ARMBaseInstrInfo*)new Thumb1InstrInfo(Subtarget))),
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DataLayout(Subtarget.isAPCS_ABI() ?
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std::string("e-p:32:32-f64:32:64-i64:32:64-"
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"i16:16:32-i8:8:32-i1:8:32-"
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"v128:32:128-v64:32:64-a:0:32-n32-S32") :
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Subtarget.isAAPCS_ABI() ?
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std::string("e-p:32:32-f64:64:64-i64:64:64-"
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"i16:16:32-i8:8:32-i1:8:32-"
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"v128:64:128-v64:64:64-a:0:32-n32-S64") :
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std::string("e-p:32:32-f64:64:64-i64:64:64-"
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"i16:16:32-i8:8:32-i1:8:32-"
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"v128:64:128-v64:64:64-a:0:32-n32-S32")),
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ELFWriterInfo(*this),
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TLInfo(*this),
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TSInfo(*this),
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FrameLowering(Subtarget.hasThumb2()
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? new ARMFrameLowering(Subtarget)
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: (ARMFrameLowering*)new Thumb1FrameLowering(Subtarget)) {
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}
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bool ARMBaseTargetMachine::addPreISel(PassManagerBase &PM,
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CodeGenOpt::Level OptLevel) {
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if (OptLevel != CodeGenOpt::None && EnableGlobalMerge)
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PM.add(createARMGlobalMergePass(getTargetLowering()));
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return false;
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}
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bool ARMBaseTargetMachine::addInstSelector(PassManagerBase &PM,
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CodeGenOpt::Level OptLevel) {
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PM.add(createARMISelDag(*this, OptLevel));
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return false;
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}
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bool ARMBaseTargetMachine::addPreRegAlloc(PassManagerBase &PM,
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CodeGenOpt::Level OptLevel) {
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// FIXME: temporarily disabling load / store optimization pass for Thumb1.
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if (OptLevel != CodeGenOpt::None && !Subtarget.isThumb1Only())
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PM.add(createARMLoadStoreOptimizationPass(true));
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if (OptLevel != CodeGenOpt::None && Subtarget.isCortexA9())
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PM.add(createMLxExpansionPass());
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return true;
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}
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bool ARMBaseTargetMachine::addPreSched2(PassManagerBase &PM,
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CodeGenOpt::Level OptLevel) {
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// FIXME: temporarily disabling load / store optimization pass for Thumb1.
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if (OptLevel != CodeGenOpt::None) {
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if (!Subtarget.isThumb1Only())
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PM.add(createARMLoadStoreOptimizationPass());
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if (Subtarget.hasNEON())
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PM.add(createExecutionDependencyFixPass(&ARM::DPRRegClass));
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}
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// Expand some pseudo instructions into multiple instructions to allow
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// proper scheduling.
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PM.add(createARMExpandPseudoPass());
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if (OptLevel != CodeGenOpt::None) {
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if (!Subtarget.isThumb1Only())
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PM.add(createIfConverterPass());
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}
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if (Subtarget.isThumb2())
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PM.add(createThumb2ITBlockPass());
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return true;
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}
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bool ARMBaseTargetMachine::addPreEmitPass(PassManagerBase &PM,
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CodeGenOpt::Level OptLevel) {
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if (Subtarget.isThumb2() && !Subtarget.prefers32BitThumb())
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PM.add(createThumb2SizeReductionPass());
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PM.add(createARMConstantIslandPass());
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return true;
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}
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bool ARMBaseTargetMachine::addCodeEmitter(PassManagerBase &PM,
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CodeGenOpt::Level OptLevel,
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JITCodeEmitter &JCE) {
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// Machine code emitter pass for ARM.
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PM.add(createARMJITCodeEmitterPass(*this, JCE));
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return false;
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}
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