David Blaikie 7c9c6ed761 [opaque pointer type] Add textual IR support for explicit type parameter to load instruction ... Essentially the same as the GEP change in r230786. A similar migration script can be used to update test cases, though a few more test case improvements/changes were required this time around: (r229269-r229278) import fileinput import sys import re pat = re.compile(r"((?:=|:|^)\s*load (?:atomic )?(?:volatile )?(.*?))(| addrspace\(\d+\) *)\*($| *(?:%|@|null|undef|blockaddress|getelementptr|addrspacecast|bitcast|inttoptr|\[\[[a-zA-Z]|\{\{).*$)") for line in sys.stdin: sys.stdout.write(re.sub(pat, r"\1, \2\3*\4", line)) Reviewers: rafael, dexonsmith, grosser Differential Revision: http://reviews.llvm.org/D7649 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@230794 91177308-0d34-0410-b5e6-96231b3b80d8		2015-02-27 21:17:42 +00:00
..
AArch64	[opaque pointer type] Add textual IR support for explicit type parameter to load instruction	2015-02-27 21:17:42 +00:00
ARM	[opaque pointer type] Add textual IR support for explicit type parameter to load instruction	2015-02-27 21:17:42 +00:00
AsmParser	MC: Don't emit .no_dead_strip on targets which don't support it	2014-12-24 04:11:42 +00:00
COFF	[opaque pointer type] Add textual IR support for explicit type parameter to load instruction	2015-02-27 21:17:42 +00:00
Disassembler	[PowerPC] Add support for the QPX vector instruction set	2015-02-25 01:06:45 +00:00
ELF	MC: Allow multiple comma-separated expressions on the .uleb128 directive.	2015-02-19 20:24:04 +00:00
Hexagon	[Hexagon] Updating predicate register transfers and adding tstbit to allow select selection. Updating ll tests with predicate transfers that previously had nop encodings.	2014-12-09 18:16:49 +00:00
MachO	[opaque pointer type] Add textual IR support for explicit type parameter to load instruction	2015-02-27 21:17:42 +00:00
Markup
Mips	[opaque pointer type] Add textual IR support for explicit type parameter to load instruction	2015-02-27 21:17:42 +00:00
PowerPC	[PowerPC] Add support for the QPX vector instruction set	2015-02-25 01:06:45 +00:00
R600	R600/SI: Add a stub GCNTargetMachine	2015-01-06 18:00:21 +00:00
Sparc
SystemZ	[SystemZ] Support all TLS access models - MC part	2015-02-18 09:11:36 +00:00
X86	[MC] Use the non-EH register mapping in the debug_frame section.	2015-02-26 19:48:07 +00:00