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48575f6ea7
difficult on current ARM implementations for a few reasons.
1. Even though a single vmla has latency that is one cycle shorter than a pair
of vmul + vadd, a RAW hazard during the first (4? on Cortex-a8) can cause
additional pipeline stall. So it's frequently better to single codegen
vmul + vadd.
2. A vmla folowed by a vmul, vmadd, or vsub causes the second fp instruction to
stall for 4 cycles. We need to schedule them apart.
3. A vmla followed vmla is a special case. Obvious issuing back to back RAW
vmla + vmla is very bad. But this isn't ideal either:
vmul
vadd
vmla
Instead, we want to expand the second vmla:
vmla
vmul
vadd
Even with the 4 cycle vmul stall, the second sequence is still 2 cycles
faster.
Up to now, isel simply avoid codegen'ing fp vmla / vmls. This works well enough
but it isn't the optimial solution. This patch attempts to make it possible to
use vmla / vmls in cases where it is profitable.
A. Add missing isel predicates which cause vmla to be codegen'ed.
B. Make sure the fmul in (fadd (fmul)) has a single use. We don't want to
compute a fmul and a fmla.
C. Add additional isel checks for vmla, avoid cases where vmla is feeding into
fp instructions (except for the #3 exceptional case).
D. Add ARM hazard recognizer to model the vmla / vmls hazards.
E. Add a special pre-regalloc case to expand vmla / vmls when it's likely the
vmla / vmls will trigger one of the special hazards.
Work in progress, only A+B are enabled.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120960 91177308-0d34-0410-b5e6-96231b3b80d8
64 lines
2.0 KiB
C++
64 lines
2.0 KiB
C++
//===-- ARM.h - Top-level interface for ARM representation---- --*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains the entry points for global functions defined in the LLVM
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// ARM back-end.
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//
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//===----------------------------------------------------------------------===//
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#ifndef TARGET_ARM_H
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#define TARGET_ARM_H
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#include "ARMBaseInfo.h"
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#include "llvm/Support/ErrorHandling.h"
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#include "llvm/Target/TargetMachine.h"
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#include <cassert>
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namespace llvm {
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class ARMBaseTargetMachine;
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class FunctionPass;
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class JITCodeEmitter;
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class formatted_raw_ostream;
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class MCCodeEmitter;
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class TargetAsmBackend;
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class MachineInstr;
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class ARMAsmPrinter;
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class MCInst;
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MCCodeEmitter *createARMMCCodeEmitter(const Target &,
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TargetMachine &TM,
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MCContext &Ctx);
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TargetAsmBackend *createARMAsmBackend(const Target &, const std::string &);
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FunctionPass *createARMISelDag(ARMBaseTargetMachine &TM,
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CodeGenOpt::Level OptLevel);
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FunctionPass *createARMJITCodeEmitterPass(ARMBaseTargetMachine &TM,
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JITCodeEmitter &JCE);
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FunctionPass *createARMLoadStoreOptimizationPass(bool PreAlloc = false);
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FunctionPass *createARMExpandPseudoPass();
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FunctionPass *createARMGlobalMergePass(const TargetLowering* tli);
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FunctionPass *createARMConstantIslandPass();
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FunctionPass *createNEONMoveFixPass();
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FunctionPass *createMLxExpansionPass();
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FunctionPass *createThumb2ITBlockPass();
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FunctionPass *createThumb2SizeReductionPass();
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extern Target TheARMTarget, TheThumbTarget;
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void LowerARMMachineInstrToMCInst(const MachineInstr *MI, MCInst &OutMI,
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ARMAsmPrinter &AP);
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} // end namespace llvm;
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#endif
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