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https://github.com/c64scene-ar/llvm-6502.git
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4e98296890
On modern cores with lfiw[az]x, we can fold a sign or zero extension from i32 to i64 into the load necessary for an i64 -> fp conversion. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225493 91177308-0d34-0410-b5e6-96231b3b80d8
70 lines
1.5 KiB
LLVM
70 lines
1.5 KiB
LLVM
; RUN: llc -mcpu=a2 < %s | FileCheck %s
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target datalayout = "E-m:e-i64:64-n32:64"
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target triple = "powerpc64-unknown-linux-gnu"
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; Function Attrs: nounwind
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define double @foo1(i32* %x) #0 {
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entry:
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%0 = load i32* %x, align 4
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%conv = sext i32 %0 to i64
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%conv1 = sitofp i64 %conv to double
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ret double %conv1
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; CHECK-LABEL: @foo1
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; CHECK: lfiwax [[REG1:[0-9]+]], 0, 3
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; CHECK: fcfid 1, [[REG1]]
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; CHECK: blr
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}
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define double @foo2(i32* %x) #0 {
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entry:
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%0 = load i32* %x, align 4
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%conv = zext i32 %0 to i64
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%conv1 = sitofp i64 %conv to double
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ret double %conv1
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; CHECK-LABEL: @foo2
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; CHECK: lfiwzx [[REG1:[0-9]+]], 0, 3
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; CHECK: fcfid 1, [[REG1]]
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; CHECK: blr
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}
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define double @foo3(i32* %x) #0 {
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entry:
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%0 = load i32* %x, align 4
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%1 = add i32 %0, 8
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%conv = zext i32 %1 to i64
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%conv1 = sitofp i64 %conv to double
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ret double %conv1
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; CHECK-LABEL: @foo3
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; CHECK-DAG: lwz [[REG1:[0-9]+]], 0(3)
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; CHECK-DAG: addi [[REG3:[0-9]+]], 1,
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; CHECK-DAG: addi [[REG2:[0-9]+]], [[REG1]], 8
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; CHECK-DAG: stw [[REG2]],
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; CHECK: lfiwzx [[REG4:[0-9]+]], 0, [[REG3]]
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; CHECK: fcfid 1, [[REG4]]
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; CHECK: blr
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}
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define double @foo4(i32* %x) #0 {
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entry:
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%0 = load i32* %x, align 4
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%1 = add i32 %0, 8
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%conv = sext i32 %1 to i64
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%conv1 = sitofp i64 %conv to double
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ret double %conv1
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; CHECK-LABEL: @foo4
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; CHECK-DAG: lwz [[REG1:[0-9]+]], 0(3)
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; CHECK-DAG: addi [[REG3:[0-9]+]], 1,
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; CHECK-DAG: addi [[REG2:[0-9]+]], [[REG1]], 8
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; CHECK-DAG: stw [[REG2]],
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; CHECK: lfiwax [[REG4:[0-9]+]], 0, [[REG3]]
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; CHECK: fcfid 1, [[REG4]]
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; CHECK: blr
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}
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attributes #0 = { nounwind }
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