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https://github.com/c64scene-ar/llvm-6502.git
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811ec1c92a
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26911 91177308-0d34-0410-b5e6-96231b3b80d8
64 lines
2.8 KiB
C++
64 lines
2.8 KiB
C++
//====- X86InstrMMX.td - Describe the X86 Instruction Set -------*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file was developed by the Evan Cheng and is distributed under
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// the University of Illinois Open Source License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file describes the X86 MMX instruction set, defining the instructions,
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// and properties of the instructions which are needed for code generation,
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// machine code emission, and analysis.
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//
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//===----------------------------------------------------------------------===//
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// Some 'special' instructions
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def IMPLICIT_DEF_VR64 : I<0, Pseudo, (ops VR64:$dst),
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"#IMPLICIT_DEF $dst",
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[(set VR64:$dst, (v8i8 (undef)))]>,
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Requires<[HasMMX]>;
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def : Pat<(v4i16 (undef)), (IMPLICIT_DEF_VR64)>, Requires<[HasMMX]>;
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def : Pat<(v2i32 (undef)), (IMPLICIT_DEF_VR64)>, Requires<[HasMMX]>;
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def SCALAR_TO_VECTOR_V8I8 : I<0, Pseudo, (ops VR64:$dst, R8:$src),
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"#SCALAR_TO_VECTOR $src",
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[(set VR64:$dst,
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(v8i8 (scalar_to_vector R8:$src)))]>,
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Requires<[HasMMX]>;
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def SCALAR_TO_VECTOR_V4I16 : I<0, Pseudo, (ops VR64:$dst, R16:$src),
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"#SCALAR_TO_VECTOR $src",
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[(set VR64:$dst,
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(v4i16 (scalar_to_vector R16:$src)))]>,
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Requires<[HasMMX]>;
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def SCALAR_TO_VECTOR_V2I32 : I<0, Pseudo, (ops VR64:$dst, R32:$src),
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"#SCALAR_TO_VECTOR $src",
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[(set VR64:$dst,
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(v2i32 (scalar_to_vector R32:$src)))]>,
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Requires<[HasMMX]>;
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// Move Instructions
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def MOVD64rr : I<0x6E, MRMSrcReg, (ops VR64:$dst, R32:$src),
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"movd {$src, $dst|$dst, $src}", []>, TB,
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Requires<[HasMMX]>;
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def MOVD64rm : I<0x6E, MRMSrcMem, (ops VR64:$dst, i32mem:$src),
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"movd {$src, $dst|$dst, $src}", []>, TB,
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Requires<[HasMMX]>;
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def MOVD64mr : I<0x7E, MRMDestMem, (ops i32mem:$dst, VR64:$src),
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"movd {$src, $dst|$dst, $src}", []>, TB,
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Requires<[HasMMX]>;
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def MOVQ64rr : I<0x6F, MRMSrcReg, (ops VR64:$dst, VR64:$src),
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"movq {$src, $dst|$dst, $src}", []>, TB,
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Requires<[HasMMX]>;
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def MOVQ64rm : I<0x6F, MRMSrcMem, (ops VR64:$dst, i64mem:$src),
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"movq {$src, $dst|$dst, $src}", []>, TB,
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Requires<[HasMMX]>;
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def MOVQ64mr : I<0x7F, MRMDestMem, (ops i64mem:$dst, VR64:$src),
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"movq {$src, $dst|$dst, $src}", []>, TB,
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Requires<[HasMMX]>;
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