mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-08-28 06:29:45 +00:00
Use sub0-15 everywhere. Patch by: Michel Dänzerr Reviewed-by: Tom Stellard <thomas.stellard@amd.com> Signed-off-by: Michel Dänzer <michel.daenzer@amd.com> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174610 91177308-0d34-0410-b5e6-96231b3b80d8
26 lines
707 B
TableGen
26 lines
707 B
TableGen
//===-- AMDGPURegisterInfo.td - AMDGPU register info -------*- tablegen -*-===//
|
|
//
|
|
// The LLVM Compiler Infrastructure
|
|
//
|
|
// This file is distributed under the University of Illinois Open Source
|
|
// License. See LICENSE.TXT for details.
|
|
//
|
|
//===----------------------------------------------------------------------===//
|
|
//
|
|
// Tablegen register definitions common to all hw codegen targets.
|
|
//
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
let Namespace = "AMDGPU" in {
|
|
|
|
foreach Index = 0-15 in {
|
|
def sub#Index : SubRegIndex;
|
|
}
|
|
|
|
def INDIRECT_BASE_ADDR : Register <"INDIRECT_BASE_ADDR">;
|
|
|
|
}
|
|
|
|
include "R600RegisterInfo.td"
|
|
include "SIRegisterInfo.td"
|