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c0b0c677a1
Only implemented for R600 so far. SI is missing implementations of a
few callbacks used by the Indirect Addressing pass and needs code to
handle frame indices.
At the moment R600 only supports array sizes of 16 dwords or less.
Register packing of vector types is currently disabled, which means that a
vec4 is stored in T0_X, T1_X, T2_X, T3_X, rather than T0_XYZW. In order
to correctly pack registers in all cases, we will need to implement an
analysis pass for R600 that determines the correct vector width for each
array.
v2:
- Add support for i8 zext load from stack.
- Coding style fixes
v3:
- Don't reserve registers for indirect addressing when it isn't
being used.
- Fix bug caused by LLVM limiting the number of SubRegIndex
declarations.
v4:
- Fix 64-bit defines
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174525 91177308-0d34-0410-b5e6-96231b3b80d8
71 lines
2.3 KiB
C++
71 lines
2.3 KiB
C++
//===-- AMDGPUTargetMachine.h - AMDGPU TargetMachine Interface --*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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/// \file
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/// \brief The AMDGPU TargetMachine interface definition for hw codgen targets.
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//
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//===----------------------------------------------------------------------===//
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#ifndef AMDGPU_TARGET_MACHINE_H
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#define AMDGPU_TARGET_MACHINE_H
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#include "AMDGPUFrameLowering.h"
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#include "AMDGPUInstrInfo.h"
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#include "AMDGPUSubtarget.h"
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#include "AMDILIntrinsicInfo.h"
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#include "R600ISelLowering.h"
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#include "llvm/ADT/OwningPtr.h"
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#include "llvm/IR/DataLayout.h"
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namespace llvm {
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MCAsmInfo* createMCAsmInfo(const Target &T, StringRef TT);
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class AMDGPUTargetMachine : public LLVMTargetMachine {
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AMDGPUSubtarget Subtarget;
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const DataLayout Layout;
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AMDGPUFrameLowering FrameLowering;
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AMDGPUIntrinsicInfo IntrinsicInfo;
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const AMDGPUInstrInfo * InstrInfo;
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AMDGPUTargetLowering * TLInfo;
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const InstrItineraryData* InstrItins;
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public:
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AMDGPUTargetMachine(const Target &T, StringRef TT, StringRef FS,
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StringRef CPU,
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TargetOptions Options,
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Reloc::Model RM, CodeModel::Model CM,
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CodeGenOpt::Level OL);
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~AMDGPUTargetMachine();
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virtual const AMDGPUFrameLowering* getFrameLowering() const {
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return &FrameLowering;
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}
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virtual const AMDGPUIntrinsicInfo* getIntrinsicInfo() const {
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return &IntrinsicInfo;
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}
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virtual const AMDGPUInstrInfo *getInstrInfo() const {return InstrInfo;}
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virtual const AMDGPUSubtarget *getSubtargetImpl() const {return &Subtarget; }
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virtual const AMDGPURegisterInfo *getRegisterInfo() const {
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return &InstrInfo->getRegisterInfo();
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}
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virtual AMDGPUTargetLowering * getTargetLowering() const {
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return TLInfo;
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}
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virtual const InstrItineraryData* getInstrItineraryData() const {
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return InstrItins;
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}
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virtual const DataLayout* getDataLayout() const { return &Layout; }
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virtual TargetPassConfig *createPassConfig(PassManagerBase &PM);
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};
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} // End namespace llvm
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#endif // AMDGPU_TARGET_MACHINE_H
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