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76fc2d077f
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182129 91177308-0d34-0410-b5e6-96231b3b80d8
59 lines
1.7 KiB
C++
59 lines
1.7 KiB
C++
//===-- R600RegisterInfo.h - R600 Register Info Interface ------*- C++ -*--===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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/// \file
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/// \brief Interface definition for R600RegisterInfo
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//
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//===----------------------------------------------------------------------===//
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#ifndef R600REGISTERINFO_H_
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#define R600REGISTERINFO_H_
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#include "AMDGPURegisterInfo.h"
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#include "AMDGPUTargetMachine.h"
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namespace llvm {
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class R600TargetMachine;
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class TargetInstrInfo;
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struct R600RegisterInfo : public AMDGPURegisterInfo {
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AMDGPUTargetMachine &TM;
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const TargetInstrInfo &TII;
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RegClassWeight RCW;
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R600RegisterInfo(AMDGPUTargetMachine &tm, const TargetInstrInfo &tii);
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virtual BitVector getReservedRegs(const MachineFunction &MF) const;
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/// \param RC is an AMDIL reg class.
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///
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/// \returns the R600 reg class that is equivalent to \p RC.
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virtual const TargetRegisterClass *getISARegClass(
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const TargetRegisterClass *RC) const;
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/// \brief get the HW encoding for a register's channel.
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unsigned getHWRegChan(unsigned reg) const;
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/// \brief get the register class of the specified type to use in the
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/// CFGStructurizer
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virtual const TargetRegisterClass * getCFGStructurizerRegClass(MVT VT) const;
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/// \returns the sub reg enum value for the given \p Channel
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/// (e.g. getSubRegFromChannel(0) -> AMDGPU::sel_x)
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unsigned getSubRegFromChannel(unsigned Channel) const;
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virtual const RegClassWeight &getRegClassWeight(const TargetRegisterClass *RC) const;
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};
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} // End namespace llvm
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#endif // AMDIDSAREGISTERINFO_H_
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