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https://github.com/c64scene-ar/llvm-6502.git
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writebacks to the address register. This gets rid of the hack that the first register on the list was the magic writeback register operand. There was an implicit constraint that if that operand was not reg0 it had to match the base register operand. The post-RA scheduler's antidependency breaker did not understand that constraint and sometimes changed one without the other. This also fixes Radar 7495976 and should help the verifier work better for ARM code. There are now new ld/st instructions explicit writeback operands and explicit constraints that tie those registers together. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98409 91177308-0d34-0410-b5e6-96231b3b80d8
2890 lines
111 KiB
TableGen
2890 lines
111 KiB
TableGen
//===- ARMInstrInfo.td - Target Description for ARM Target -*- tablegen -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file describes the ARM instructions in TableGen format.
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//
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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// ARM specific DAG Nodes.
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//
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// Type profiles.
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def SDT_ARMCallSeqStart : SDCallSeqStart<[ SDTCisVT<0, i32> ]>;
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def SDT_ARMCallSeqEnd : SDCallSeqEnd<[ SDTCisVT<0, i32>, SDTCisVT<1, i32> ]>;
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def SDT_ARMSaveCallPC : SDTypeProfile<0, 1, []>;
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def SDT_ARMcall : SDTypeProfile<0, -1, [SDTCisPtrTy<0>]>;
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def SDT_ARMCMov : SDTypeProfile<1, 3,
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[SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>,
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SDTCisVT<3, i32>]>;
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def SDT_ARMBrcond : SDTypeProfile<0, 2,
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[SDTCisVT<0, OtherVT>, SDTCisVT<1, i32>]>;
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def SDT_ARMBrJT : SDTypeProfile<0, 3,
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[SDTCisPtrTy<0>, SDTCisVT<1, i32>,
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SDTCisVT<2, i32>]>;
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def SDT_ARMBr2JT : SDTypeProfile<0, 4,
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[SDTCisPtrTy<0>, SDTCisVT<1, i32>,
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SDTCisVT<2, i32>, SDTCisVT<3, i32>]>;
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def SDT_ARMCmp : SDTypeProfile<0, 2, [SDTCisSameAs<0, 1>]>;
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def SDT_ARMPICAdd : SDTypeProfile<1, 2, [SDTCisSameAs<0, 1>,
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SDTCisPtrTy<1>, SDTCisVT<2, i32>]>;
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def SDT_ARMThreadPointer : SDTypeProfile<1, 0, [SDTCisPtrTy<0>]>;
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def SDT_ARMEH_SJLJ_Setjmp : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisPtrTy<1>,
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SDTCisInt<2>]>;
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def SDT_ARMMEMBARRIERV7 : SDTypeProfile<0, 0, []>;
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def SDT_ARMSYNCBARRIERV7 : SDTypeProfile<0, 0, []>;
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def SDT_ARMMEMBARRIERV6 : SDTypeProfile<0, 1, [SDTCisInt<0>]>;
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def SDT_ARMSYNCBARRIERV6 : SDTypeProfile<0, 1, [SDTCisInt<0>]>;
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// Node definitions.
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def ARMWrapper : SDNode<"ARMISD::Wrapper", SDTIntUnaryOp>;
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def ARMWrapperJT : SDNode<"ARMISD::WrapperJT", SDTIntBinOp>;
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def ARMcallseq_start : SDNode<"ISD::CALLSEQ_START", SDT_ARMCallSeqStart,
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[SDNPHasChain, SDNPOutFlag]>;
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def ARMcallseq_end : SDNode<"ISD::CALLSEQ_END", SDT_ARMCallSeqEnd,
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[SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
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def ARMcall : SDNode<"ARMISD::CALL", SDT_ARMcall,
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[SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
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def ARMcall_pred : SDNode<"ARMISD::CALL_PRED", SDT_ARMcall,
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[SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
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def ARMcall_nolink : SDNode<"ARMISD::CALL_NOLINK", SDT_ARMcall,
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[SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
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def ARMretflag : SDNode<"ARMISD::RET_FLAG", SDTNone,
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[SDNPHasChain, SDNPOptInFlag]>;
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def ARMcmov : SDNode<"ARMISD::CMOV", SDT_ARMCMov,
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[SDNPInFlag]>;
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def ARMcneg : SDNode<"ARMISD::CNEG", SDT_ARMCMov,
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[SDNPInFlag]>;
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def ARMbrcond : SDNode<"ARMISD::BRCOND", SDT_ARMBrcond,
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[SDNPHasChain, SDNPInFlag, SDNPOutFlag]>;
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def ARMbrjt : SDNode<"ARMISD::BR_JT", SDT_ARMBrJT,
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[SDNPHasChain]>;
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def ARMbr2jt : SDNode<"ARMISD::BR2_JT", SDT_ARMBr2JT,
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[SDNPHasChain]>;
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def ARMcmp : SDNode<"ARMISD::CMP", SDT_ARMCmp,
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[SDNPOutFlag]>;
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def ARMcmpZ : SDNode<"ARMISD::CMPZ", SDT_ARMCmp,
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[SDNPOutFlag,SDNPCommutative]>;
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def ARMpic_add : SDNode<"ARMISD::PIC_ADD", SDT_ARMPICAdd>;
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def ARMsrl_flag : SDNode<"ARMISD::SRL_FLAG", SDTIntUnaryOp, [SDNPOutFlag]>;
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def ARMsra_flag : SDNode<"ARMISD::SRA_FLAG", SDTIntUnaryOp, [SDNPOutFlag]>;
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def ARMrrx : SDNode<"ARMISD::RRX" , SDTIntUnaryOp, [SDNPInFlag ]>;
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def ARMthread_pointer: SDNode<"ARMISD::THREAD_POINTER", SDT_ARMThreadPointer>;
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def ARMeh_sjlj_setjmp: SDNode<"ARMISD::EH_SJLJ_SETJMP", SDT_ARMEH_SJLJ_Setjmp>;
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def ARMMemBarrierV7 : SDNode<"ARMISD::MEMBARRIER", SDT_ARMMEMBARRIERV7,
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[SDNPHasChain]>;
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def ARMSyncBarrierV7 : SDNode<"ARMISD::SYNCBARRIER", SDT_ARMMEMBARRIERV7,
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[SDNPHasChain]>;
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def ARMMemBarrierV6 : SDNode<"ARMISD::MEMBARRIER", SDT_ARMMEMBARRIERV6,
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[SDNPHasChain]>;
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def ARMSyncBarrierV6 : SDNode<"ARMISD::SYNCBARRIER", SDT_ARMMEMBARRIERV6,
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[SDNPHasChain]>;
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def ARMrbit : SDNode<"ARMISD::RBIT", SDTIntUnaryOp>;
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//===----------------------------------------------------------------------===//
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// ARM Instruction Predicate Definitions.
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//
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def HasV4T : Predicate<"Subtarget->hasV4TOps()">;
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def NoV4T : Predicate<"!Subtarget->hasV4TOps()">;
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def HasV5T : Predicate<"Subtarget->hasV5TOps()">;
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def HasV5TE : Predicate<"Subtarget->hasV5TEOps()">;
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def HasV6 : Predicate<"Subtarget->hasV6Ops()">;
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def HasV6T2 : Predicate<"Subtarget->hasV6T2Ops()">;
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def NoV6T2 : Predicate<"!Subtarget->hasV6T2Ops()">;
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def HasV7 : Predicate<"Subtarget->hasV7Ops()">;
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def HasVFP2 : Predicate<"Subtarget->hasVFP2()">;
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def HasVFP3 : Predicate<"Subtarget->hasVFP3()">;
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def HasNEON : Predicate<"Subtarget->hasNEON()">;
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def UseNEONForFP : Predicate<"Subtarget->useNEONForSinglePrecisionFP()">;
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def DontUseNEONForFP : Predicate<"!Subtarget->useNEONForSinglePrecisionFP()">;
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def IsThumb : Predicate<"Subtarget->isThumb()">;
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def IsThumb1Only : Predicate<"Subtarget->isThumb1Only()">;
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def IsThumb2 : Predicate<"Subtarget->isThumb2()">;
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def IsARM : Predicate<"!Subtarget->isThumb()">;
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def IsDarwin : Predicate<"Subtarget->isTargetDarwin()">;
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def IsNotDarwin : Predicate<"!Subtarget->isTargetDarwin()">;
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// FIXME: Eventually this will be just "hasV6T2Ops".
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def UseMovt : Predicate<"Subtarget->useMovt()">;
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def DontUseMovt : Predicate<"!Subtarget->useMovt()">;
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//===----------------------------------------------------------------------===//
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// ARM Flag Definitions.
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class RegConstraint<string C> {
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string Constraints = C;
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}
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//===----------------------------------------------------------------------===//
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// ARM specific transformation functions and pattern fragments.
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//
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// so_imm_neg_XFORM - Return a so_imm value packed into the format described for
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// so_imm_neg def below.
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def so_imm_neg_XFORM : SDNodeXForm<imm, [{
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return CurDAG->getTargetConstant(-(int)N->getZExtValue(), MVT::i32);
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}]>;
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// so_imm_not_XFORM - Return a so_imm value packed into the format described for
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// so_imm_not def below.
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def so_imm_not_XFORM : SDNodeXForm<imm, [{
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return CurDAG->getTargetConstant(~(int)N->getZExtValue(), MVT::i32);
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}]>;
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// rot_imm predicate - True if the 32-bit immediate is equal to 8, 16, or 24.
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def rot_imm : PatLeaf<(i32 imm), [{
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int32_t v = (int32_t)N->getZExtValue();
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return v == 8 || v == 16 || v == 24;
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}]>;
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/// imm1_15 predicate - True if the 32-bit immediate is in the range [1,15].
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def imm1_15 : PatLeaf<(i32 imm), [{
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return (int32_t)N->getZExtValue() >= 1 && (int32_t)N->getZExtValue() < 16;
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}]>;
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/// imm16_31 predicate - True if the 32-bit immediate is in the range [16,31].
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def imm16_31 : PatLeaf<(i32 imm), [{
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return (int32_t)N->getZExtValue() >= 16 && (int32_t)N->getZExtValue() < 32;
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}]>;
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def so_imm_neg :
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PatLeaf<(imm), [{
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return ARM_AM::getSOImmVal(-(int)N->getZExtValue()) != -1;
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}], so_imm_neg_XFORM>;
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def so_imm_not :
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PatLeaf<(imm), [{
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return ARM_AM::getSOImmVal(~(int)N->getZExtValue()) != -1;
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}], so_imm_not_XFORM>;
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// sext_16_node predicate - True if the SDNode is sign-extended 16 or more bits.
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def sext_16_node : PatLeaf<(i32 GPR:$a), [{
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return CurDAG->ComputeNumSignBits(SDValue(N,0)) >= 17;
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}]>;
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/// bf_inv_mask_imm predicate - An AND mask to clear an arbitrary width bitfield
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/// e.g., 0xf000ffff
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def bf_inv_mask_imm : Operand<i32>,
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PatLeaf<(imm), [{
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uint32_t v = (uint32_t)N->getZExtValue();
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if (v == 0xffffffff)
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return 0;
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// there can be 1's on either or both "outsides", all the "inside"
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// bits must be 0's
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unsigned int lsb = 0, msb = 31;
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while (v & (1 << msb)) --msb;
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while (v & (1 << lsb)) ++lsb;
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for (unsigned int i = lsb; i <= msb; ++i) {
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if (v & (1 << i))
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return 0;
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}
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return 1;
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}] > {
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let PrintMethod = "printBitfieldInvMaskImmOperand";
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}
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/// Split a 32-bit immediate into two 16 bit parts.
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def lo16 : SDNodeXForm<imm, [{
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return CurDAG->getTargetConstant((uint32_t)N->getZExtValue() & 0xffff,
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MVT::i32);
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}]>;
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def hi16 : SDNodeXForm<imm, [{
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return CurDAG->getTargetConstant((uint32_t)N->getZExtValue() >> 16, MVT::i32);
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}]>;
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def lo16AllZero : PatLeaf<(i32 imm), [{
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// Returns true if all low 16-bits are 0.
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return (((uint32_t)N->getZExtValue()) & 0xFFFFUL) == 0;
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}], hi16>;
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/// imm0_65535 predicate - True if the 32-bit immediate is in the range
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/// [0.65535].
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def imm0_65535 : PatLeaf<(i32 imm), [{
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return (uint32_t)N->getZExtValue() < 65536;
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}]>;
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class BinOpFrag<dag res> : PatFrag<(ops node:$LHS, node:$RHS), res>;
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class UnOpFrag <dag res> : PatFrag<(ops node:$Src), res>;
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/// adde and sube predicates - True based on whether the carry flag output
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/// will be needed or not.
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def adde_dead_carry :
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PatFrag<(ops node:$LHS, node:$RHS), (adde node:$LHS, node:$RHS),
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[{return !N->hasAnyUseOfValue(1);}]>;
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def sube_dead_carry :
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PatFrag<(ops node:$LHS, node:$RHS), (sube node:$LHS, node:$RHS),
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[{return !N->hasAnyUseOfValue(1);}]>;
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def adde_live_carry :
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PatFrag<(ops node:$LHS, node:$RHS), (adde node:$LHS, node:$RHS),
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[{return N->hasAnyUseOfValue(1);}]>;
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def sube_live_carry :
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PatFrag<(ops node:$LHS, node:$RHS), (sube node:$LHS, node:$RHS),
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[{return N->hasAnyUseOfValue(1);}]>;
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//===----------------------------------------------------------------------===//
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// Operand Definitions.
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//
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// Branch target.
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def brtarget : Operand<OtherVT>;
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// A list of registers separated by comma. Used by load/store multiple.
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def reglist : Operand<i32> {
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let PrintMethod = "printRegisterList";
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}
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// An operand for the CONSTPOOL_ENTRY pseudo-instruction.
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def cpinst_operand : Operand<i32> {
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let PrintMethod = "printCPInstOperand";
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}
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def jtblock_operand : Operand<i32> {
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let PrintMethod = "printJTBlockOperand";
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}
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def jt2block_operand : Operand<i32> {
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let PrintMethod = "printJT2BlockOperand";
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}
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// Local PC labels.
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def pclabel : Operand<i32> {
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let PrintMethod = "printPCLabel";
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}
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// shifter_operand operands: so_reg and so_imm.
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def so_reg : Operand<i32>, // reg reg imm
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ComplexPattern<i32, 3, "SelectShifterOperandReg",
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[shl,srl,sra,rotr]> {
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let PrintMethod = "printSORegOperand";
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let MIOperandInfo = (ops GPR, GPR, i32imm);
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}
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// so_imm - Match a 32-bit shifter_operand immediate operand, which is an
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// 8-bit immediate rotated by an arbitrary number of bits. so_imm values are
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// represented in the imm field in the same 12-bit form that they are encoded
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// into so_imm instructions: the 8-bit immediate is the least significant bits
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// [bits 0-7], the 4-bit shift amount is the next 4 bits [bits 8-11].
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def so_imm : Operand<i32>,
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PatLeaf<(imm), [{
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return ARM_AM::getSOImmVal(N->getZExtValue()) != -1;
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}]> {
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let PrintMethod = "printSOImmOperand";
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}
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// Break so_imm's up into two pieces. This handles immediates with up to 16
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// bits set in them. This uses so_imm2part to match and so_imm2part_[12] to
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// get the first/second pieces.
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def so_imm2part : Operand<i32>,
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PatLeaf<(imm), [{
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return ARM_AM::isSOImmTwoPartVal((unsigned)N->getZExtValue());
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}]> {
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let PrintMethod = "printSOImm2PartOperand";
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}
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def so_imm2part_1 : SDNodeXForm<imm, [{
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unsigned V = ARM_AM::getSOImmTwoPartFirst((unsigned)N->getZExtValue());
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return CurDAG->getTargetConstant(V, MVT::i32);
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}]>;
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def so_imm2part_2 : SDNodeXForm<imm, [{
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unsigned V = ARM_AM::getSOImmTwoPartSecond((unsigned)N->getZExtValue());
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return CurDAG->getTargetConstant(V, MVT::i32);
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}]>;
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def so_neg_imm2part : Operand<i32>, PatLeaf<(imm), [{
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return ARM_AM::isSOImmTwoPartVal(-(int)N->getZExtValue());
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}]> {
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let PrintMethod = "printSOImm2PartOperand";
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}
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def so_neg_imm2part_1 : SDNodeXForm<imm, [{
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unsigned V = ARM_AM::getSOImmTwoPartFirst(-(int)N->getZExtValue());
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return CurDAG->getTargetConstant(V, MVT::i32);
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}]>;
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def so_neg_imm2part_2 : SDNodeXForm<imm, [{
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unsigned V = ARM_AM::getSOImmTwoPartSecond(-(int)N->getZExtValue());
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return CurDAG->getTargetConstant(V, MVT::i32);
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}]>;
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/// imm0_31 predicate - True if the 32-bit immediate is in the range [0,31].
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def imm0_31 : Operand<i32>, PatLeaf<(imm), [{
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return (int32_t)N->getZExtValue() < 32;
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}]>;
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// Define ARM specific addressing modes.
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// addrmode2 := reg +/- reg shop imm
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// addrmode2 := reg +/- imm12
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//
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def addrmode2 : Operand<i32>,
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ComplexPattern<i32, 3, "SelectAddrMode2", []> {
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let PrintMethod = "printAddrMode2Operand";
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let MIOperandInfo = (ops GPR:$base, GPR:$offsreg, i32imm:$offsimm);
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}
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def am2offset : Operand<i32>,
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ComplexPattern<i32, 2, "SelectAddrMode2Offset", []> {
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let PrintMethod = "printAddrMode2OffsetOperand";
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let MIOperandInfo = (ops GPR, i32imm);
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}
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// addrmode3 := reg +/- reg
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// addrmode3 := reg +/- imm8
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//
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def addrmode3 : Operand<i32>,
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ComplexPattern<i32, 3, "SelectAddrMode3", []> {
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let PrintMethod = "printAddrMode3Operand";
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let MIOperandInfo = (ops GPR:$base, GPR:$offsreg, i32imm:$offsimm);
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}
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def am3offset : Operand<i32>,
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ComplexPattern<i32, 2, "SelectAddrMode3Offset", []> {
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let PrintMethod = "printAddrMode3OffsetOperand";
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let MIOperandInfo = (ops GPR, i32imm);
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}
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// addrmode4 := reg, <mode|W>
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//
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def addrmode4 : Operand<i32>,
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ComplexPattern<i32, 2, "SelectAddrMode4", []> {
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let PrintMethod = "printAddrMode4Operand";
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let MIOperandInfo = (ops GPR:$addr, i32imm);
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}
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// addrmode5 := reg +/- imm8*4
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//
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def addrmode5 : Operand<i32>,
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ComplexPattern<i32, 2, "SelectAddrMode5", []> {
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let PrintMethod = "printAddrMode5Operand";
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let MIOperandInfo = (ops GPR:$base, i32imm);
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}
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// addrmode6 := reg with optional writeback
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//
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def addrmode6 : Operand<i32>,
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ComplexPattern<i32, 4, "SelectAddrMode6", []> {
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let PrintMethod = "printAddrMode6Operand";
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let MIOperandInfo = (ops GPR:$addr, GPR:$upd, i32imm, i32imm);
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}
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// addrmodepc := pc + reg
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//
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def addrmodepc : Operand<i32>,
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ComplexPattern<i32, 2, "SelectAddrModePC", []> {
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let PrintMethod = "printAddrModePCOperand";
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let MIOperandInfo = (ops GPR, i32imm);
|
|
}
|
|
|
|
def nohash_imm : Operand<i32> {
|
|
let PrintMethod = "printNoHashImmediate";
|
|
}
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
include "ARMInstrFormats.td"
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// Multiclass helpers...
|
|
//
|
|
|
|
/// AsI1_bin_irs - Defines a set of (op r, {so_imm|r|so_reg}) patterns for a
|
|
/// binop that produces a value.
|
|
multiclass AsI1_bin_irs<bits<4> opcod, string opc, PatFrag opnode,
|
|
bit Commutable = 0> {
|
|
def ri : AsI1<opcod, (outs GPR:$dst), (ins GPR:$a, so_imm:$b), DPFrm,
|
|
IIC_iALUi, opc, "\t$dst, $a, $b",
|
|
[(set GPR:$dst, (opnode GPR:$a, so_imm:$b))]> {
|
|
let Inst{25} = 1;
|
|
}
|
|
def rr : AsI1<opcod, (outs GPR:$dst), (ins GPR:$a, GPR:$b), DPFrm,
|
|
IIC_iALUr, opc, "\t$dst, $a, $b",
|
|
[(set GPR:$dst, (opnode GPR:$a, GPR:$b))]> {
|
|
let Inst{11-4} = 0b00000000;
|
|
let Inst{25} = 0;
|
|
let isCommutable = Commutable;
|
|
}
|
|
def rs : AsI1<opcod, (outs GPR:$dst), (ins GPR:$a, so_reg:$b), DPSoRegFrm,
|
|
IIC_iALUsr, opc, "\t$dst, $a, $b",
|
|
[(set GPR:$dst, (opnode GPR:$a, so_reg:$b))]> {
|
|
let Inst{25} = 0;
|
|
}
|
|
}
|
|
|
|
/// AI1_bin_s_irs - Similar to AsI1_bin_irs except it sets the 's' bit so the
|
|
/// instruction modifies the CPSR register.
|
|
let Defs = [CPSR] in {
|
|
multiclass AI1_bin_s_irs<bits<4> opcod, string opc, PatFrag opnode,
|
|
bit Commutable = 0> {
|
|
def ri : AI1<opcod, (outs GPR:$dst), (ins GPR:$a, so_imm:$b), DPFrm,
|
|
IIC_iALUi, opc, "\t$dst, $a, $b",
|
|
[(set GPR:$dst, (opnode GPR:$a, so_imm:$b))]> {
|
|
let Inst{20} = 1;
|
|
let Inst{25} = 1;
|
|
}
|
|
def rr : AI1<opcod, (outs GPR:$dst), (ins GPR:$a, GPR:$b), DPFrm,
|
|
IIC_iALUr, opc, "\t$dst, $a, $b",
|
|
[(set GPR:$dst, (opnode GPR:$a, GPR:$b))]> {
|
|
let isCommutable = Commutable;
|
|
let Inst{11-4} = 0b00000000;
|
|
let Inst{20} = 1;
|
|
let Inst{25} = 0;
|
|
}
|
|
def rs : AI1<opcod, (outs GPR:$dst), (ins GPR:$a, so_reg:$b), DPSoRegFrm,
|
|
IIC_iALUsr, opc, "\t$dst, $a, $b",
|
|
[(set GPR:$dst, (opnode GPR:$a, so_reg:$b))]> {
|
|
let Inst{20} = 1;
|
|
let Inst{25} = 0;
|
|
}
|
|
}
|
|
}
|
|
|
|
/// AI1_cmp_irs - Defines a set of (op r, {so_imm|r|so_reg}) cmp / test
|
|
/// patterns. Similar to AsI1_bin_irs except the instruction does not produce
|
|
/// a explicit result, only implicitly set CPSR.
|
|
let Defs = [CPSR] in {
|
|
multiclass AI1_cmp_irs<bits<4> opcod, string opc, PatFrag opnode,
|
|
bit Commutable = 0> {
|
|
def ri : AI1<opcod, (outs), (ins GPR:$a, so_imm:$b), DPFrm, IIC_iCMPi,
|
|
opc, "\t$a, $b",
|
|
[(opnode GPR:$a, so_imm:$b)]> {
|
|
let Inst{20} = 1;
|
|
let Inst{25} = 1;
|
|
}
|
|
def rr : AI1<opcod, (outs), (ins GPR:$a, GPR:$b), DPFrm, IIC_iCMPr,
|
|
opc, "\t$a, $b",
|
|
[(opnode GPR:$a, GPR:$b)]> {
|
|
let Inst{11-4} = 0b00000000;
|
|
let Inst{20} = 1;
|
|
let Inst{25} = 0;
|
|
let isCommutable = Commutable;
|
|
}
|
|
def rs : AI1<opcod, (outs), (ins GPR:$a, so_reg:$b), DPSoRegFrm, IIC_iCMPsr,
|
|
opc, "\t$a, $b",
|
|
[(opnode GPR:$a, so_reg:$b)]> {
|
|
let Inst{20} = 1;
|
|
let Inst{25} = 0;
|
|
}
|
|
}
|
|
}
|
|
|
|
/// AI_unary_rrot - A unary operation with two forms: one whose operand is a
|
|
/// register and one whose operand is a register rotated by 8/16/24.
|
|
/// FIXME: Remove the 'r' variant. Its rot_imm is zero.
|
|
multiclass AI_unary_rrot<bits<8> opcod, string opc, PatFrag opnode> {
|
|
def r : AExtI<opcod, (outs GPR:$dst), (ins GPR:$src),
|
|
IIC_iUNAr, opc, "\t$dst, $src",
|
|
[(set GPR:$dst, (opnode GPR:$src))]>,
|
|
Requires<[IsARM, HasV6]> {
|
|
let Inst{11-10} = 0b00;
|
|
let Inst{19-16} = 0b1111;
|
|
}
|
|
def r_rot : AExtI<opcod, (outs GPR:$dst), (ins GPR:$src, i32imm:$rot),
|
|
IIC_iUNAsi, opc, "\t$dst, $src, ror $rot",
|
|
[(set GPR:$dst, (opnode (rotr GPR:$src, rot_imm:$rot)))]>,
|
|
Requires<[IsARM, HasV6]> {
|
|
let Inst{19-16} = 0b1111;
|
|
}
|
|
}
|
|
|
|
multiclass AI_unary_rrot_np<bits<8> opcod, string opc> {
|
|
def r : AExtI<opcod, (outs GPR:$dst), (ins GPR:$src),
|
|
IIC_iUNAr, opc, "\t$dst, $src",
|
|
[/* For disassembly only; pattern left blank */]>,
|
|
Requires<[IsARM, HasV6]> {
|
|
let Inst{11-10} = 0b00;
|
|
let Inst{19-16} = 0b1111;
|
|
}
|
|
def r_rot : AExtI<opcod, (outs GPR:$dst), (ins GPR:$src, i32imm:$rot),
|
|
IIC_iUNAsi, opc, "\t$dst, $src, ror $rot",
|
|
[/* For disassembly only; pattern left blank */]>,
|
|
Requires<[IsARM, HasV6]> {
|
|
let Inst{19-16} = 0b1111;
|
|
}
|
|
}
|
|
|
|
/// AI_bin_rrot - A binary operation with two forms: one whose operand is a
|
|
/// register and one whose operand is a register rotated by 8/16/24.
|
|
multiclass AI_bin_rrot<bits<8> opcod, string opc, PatFrag opnode> {
|
|
def rr : AExtI<opcod, (outs GPR:$dst), (ins GPR:$LHS, GPR:$RHS),
|
|
IIC_iALUr, opc, "\t$dst, $LHS, $RHS",
|
|
[(set GPR:$dst, (opnode GPR:$LHS, GPR:$RHS))]>,
|
|
Requires<[IsARM, HasV6]> {
|
|
let Inst{11-10} = 0b00;
|
|
}
|
|
def rr_rot : AExtI<opcod, (outs GPR:$dst), (ins GPR:$LHS, GPR:$RHS,
|
|
i32imm:$rot),
|
|
IIC_iALUsi, opc, "\t$dst, $LHS, $RHS, ror $rot",
|
|
[(set GPR:$dst, (opnode GPR:$LHS,
|
|
(rotr GPR:$RHS, rot_imm:$rot)))]>,
|
|
Requires<[IsARM, HasV6]>;
|
|
}
|
|
|
|
// For disassembly only.
|
|
multiclass AI_bin_rrot_np<bits<8> opcod, string opc> {
|
|
def rr : AExtI<opcod, (outs GPR:$dst), (ins GPR:$LHS, GPR:$RHS),
|
|
IIC_iALUr, opc, "\t$dst, $LHS, $RHS",
|
|
[/* For disassembly only; pattern left blank */]>,
|
|
Requires<[IsARM, HasV6]> {
|
|
let Inst{11-10} = 0b00;
|
|
}
|
|
def rr_rot : AExtI<opcod, (outs GPR:$dst), (ins GPR:$LHS, GPR:$RHS,
|
|
i32imm:$rot),
|
|
IIC_iALUsi, opc, "\t$dst, $LHS, $RHS, ror $rot",
|
|
[/* For disassembly only; pattern left blank */]>,
|
|
Requires<[IsARM, HasV6]>;
|
|
}
|
|
|
|
/// AI1_adde_sube_irs - Define instructions and patterns for adde and sube.
|
|
let Uses = [CPSR] in {
|
|
multiclass AI1_adde_sube_irs<bits<4> opcod, string opc, PatFrag opnode,
|
|
bit Commutable = 0> {
|
|
def ri : AsI1<opcod, (outs GPR:$dst), (ins GPR:$a, so_imm:$b),
|
|
DPFrm, IIC_iALUi, opc, "\t$dst, $a, $b",
|
|
[(set GPR:$dst, (opnode GPR:$a, so_imm:$b))]>,
|
|
Requires<[IsARM]> {
|
|
let Inst{25} = 1;
|
|
}
|
|
def rr : AsI1<opcod, (outs GPR:$dst), (ins GPR:$a, GPR:$b),
|
|
DPFrm, IIC_iALUr, opc, "\t$dst, $a, $b",
|
|
[(set GPR:$dst, (opnode GPR:$a, GPR:$b))]>,
|
|
Requires<[IsARM]> {
|
|
let isCommutable = Commutable;
|
|
let Inst{11-4} = 0b00000000;
|
|
let Inst{25} = 0;
|
|
}
|
|
def rs : AsI1<opcod, (outs GPR:$dst), (ins GPR:$a, so_reg:$b),
|
|
DPSoRegFrm, IIC_iALUsr, opc, "\t$dst, $a, $b",
|
|
[(set GPR:$dst, (opnode GPR:$a, so_reg:$b))]>,
|
|
Requires<[IsARM]> {
|
|
let Inst{25} = 0;
|
|
}
|
|
}
|
|
// Carry setting variants
|
|
let Defs = [CPSR] in {
|
|
multiclass AI1_adde_sube_s_irs<bits<4> opcod, string opc, PatFrag opnode,
|
|
bit Commutable = 0> {
|
|
def Sri : AXI1<opcod, (outs GPR:$dst), (ins GPR:$a, so_imm:$b),
|
|
DPFrm, IIC_iALUi, !strconcat(opc, "\t$dst, $a, $b"),
|
|
[(set GPR:$dst, (opnode GPR:$a, so_imm:$b))]>,
|
|
Requires<[IsARM]> {
|
|
let Inst{20} = 1;
|
|
let Inst{25} = 1;
|
|
}
|
|
def Srr : AXI1<opcod, (outs GPR:$dst), (ins GPR:$a, GPR:$b),
|
|
DPFrm, IIC_iALUr, !strconcat(opc, "\t$dst, $a, $b"),
|
|
[(set GPR:$dst, (opnode GPR:$a, GPR:$b))]>,
|
|
Requires<[IsARM]> {
|
|
let Inst{11-4} = 0b00000000;
|
|
let Inst{20} = 1;
|
|
let Inst{25} = 0;
|
|
}
|
|
def Srs : AXI1<opcod, (outs GPR:$dst), (ins GPR:$a, so_reg:$b),
|
|
DPSoRegFrm, IIC_iALUsr, !strconcat(opc, "\t$dst, $a, $b"),
|
|
[(set GPR:$dst, (opnode GPR:$a, so_reg:$b))]>,
|
|
Requires<[IsARM]> {
|
|
let Inst{20} = 1;
|
|
let Inst{25} = 0;
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// Instructions
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// Miscellaneous Instructions.
|
|
//
|
|
|
|
/// CONSTPOOL_ENTRY - This instruction represents a floating constant pool in
|
|
/// the function. The first operand is the ID# for this instruction, the second
|
|
/// is the index into the MachineConstantPool that this is, the third is the
|
|
/// size in bytes of this constant pool entry.
|
|
let neverHasSideEffects = 1, isNotDuplicable = 1 in
|
|
def CONSTPOOL_ENTRY :
|
|
PseudoInst<(outs), (ins cpinst_operand:$instid, cpinst_operand:$cpidx,
|
|
i32imm:$size), NoItinerary,
|
|
"${instid:label} ${cpidx:cpentry}", []>;
|
|
|
|
// FIXME: Marking these as hasSideEffects is necessary to prevent machine DCE
|
|
// from removing one half of the matched pairs. That breaks PEI, which assumes
|
|
// these will always be in pairs, and asserts if it finds otherwise. Better way?
|
|
let Defs = [SP], Uses = [SP], hasSideEffects = 1 in {
|
|
def ADJCALLSTACKUP :
|
|
PseudoInst<(outs), (ins i32imm:$amt1, i32imm:$amt2, pred:$p), NoItinerary,
|
|
"@ ADJCALLSTACKUP $amt1",
|
|
[(ARMcallseq_end timm:$amt1, timm:$amt2)]>;
|
|
|
|
def ADJCALLSTACKDOWN :
|
|
PseudoInst<(outs), (ins i32imm:$amt, pred:$p), NoItinerary,
|
|
"@ ADJCALLSTACKDOWN $amt",
|
|
[(ARMcallseq_start timm:$amt)]>;
|
|
}
|
|
|
|
def NOP : AI<(outs), (ins), MiscFrm, NoItinerary, "nop", "",
|
|
[/* For disassembly only; pattern left blank */]>,
|
|
Requires<[IsARM, HasV6T2]> {
|
|
let Inst{27-16} = 0b001100100000;
|
|
let Inst{7-0} = 0b00000000;
|
|
}
|
|
|
|
def YIELD : AI<(outs), (ins), MiscFrm, NoItinerary, "yield", "",
|
|
[/* For disassembly only; pattern left blank */]>,
|
|
Requires<[IsARM, HasV6T2]> {
|
|
let Inst{27-16} = 0b001100100000;
|
|
let Inst{7-0} = 0b00000001;
|
|
}
|
|
|
|
def WFE : AI<(outs), (ins), MiscFrm, NoItinerary, "wfe", "",
|
|
[/* For disassembly only; pattern left blank */]>,
|
|
Requires<[IsARM, HasV6T2]> {
|
|
let Inst{27-16} = 0b001100100000;
|
|
let Inst{7-0} = 0b00000010;
|
|
}
|
|
|
|
def WFI : AI<(outs), (ins), MiscFrm, NoItinerary, "wfi", "",
|
|
[/* For disassembly only; pattern left blank */]>,
|
|
Requires<[IsARM, HasV6T2]> {
|
|
let Inst{27-16} = 0b001100100000;
|
|
let Inst{7-0} = 0b00000011;
|
|
}
|
|
|
|
def SEL : AI<(outs GPR:$dst), (ins GPR:$a, GPR:$b), DPFrm, NoItinerary, "sel",
|
|
"\t$dst, $a, $b",
|
|
[/* For disassembly only; pattern left blank */]>,
|
|
Requires<[IsARM, HasV6]> {
|
|
let Inst{27-20} = 0b01101000;
|
|
let Inst{7-4} = 0b1011;
|
|
}
|
|
|
|
def SEV : AI<(outs), (ins), MiscFrm, NoItinerary, "sev", "",
|
|
[/* For disassembly only; pattern left blank */]>,
|
|
Requires<[IsARM, HasV6T2]> {
|
|
let Inst{27-16} = 0b001100100000;
|
|
let Inst{7-0} = 0b00000100;
|
|
}
|
|
|
|
// The i32imm operand $val can be used by a debugger to store more information
|
|
// about the breakpoint.
|
|
def BKPT : AI<(outs), (ins i32imm:$val), MiscFrm, NoItinerary, "bkpt", "\t$val",
|
|
[/* For disassembly only; pattern left blank */]>,
|
|
Requires<[IsARM]> {
|
|
let Inst{27-20} = 0b00010010;
|
|
let Inst{7-4} = 0b0111;
|
|
}
|
|
|
|
// Change Processor State is a system instruction -- for disassembly only.
|
|
// The singleton $opt operand contains the following information:
|
|
// opt{4-0} = mode from Inst{4-0}
|
|
// opt{5} = changemode from Inst{17}
|
|
// opt{8-6} = AIF from Inst{8-6}
|
|
// opt{10-9} = imod from Inst{19-18} with 0b10 as enable and 0b11 as disable
|
|
def CPS : AXI<(outs), (ins cps_opt:$opt), MiscFrm, NoItinerary, "cps$opt",
|
|
[/* For disassembly only; pattern left blank */]>,
|
|
Requires<[IsARM]> {
|
|
let Inst{31-28} = 0b1111;
|
|
let Inst{27-20} = 0b00010000;
|
|
let Inst{16} = 0;
|
|
let Inst{5} = 0;
|
|
}
|
|
|
|
// Preload signals the memory system of possible future data/instruction access.
|
|
// These are for disassembly only.
|
|
//
|
|
// A8.6.117, A8.6.118. Different instructions are generated for #0 and #-0.
|
|
// The neg_zero operand translates -0 to -1, -1 to -2, ..., etc.
|
|
multiclass APreLoad<bit data, bit read, string opc> {
|
|
|
|
def i : AXI<(outs), (ins GPR:$base, neg_zero:$imm), MiscFrm, NoItinerary,
|
|
!strconcat(opc, "\t[$base, $imm]"), []> {
|
|
let Inst{31-26} = 0b111101;
|
|
let Inst{25} = 0; // 0 for immediate form
|
|
let Inst{24} = data;
|
|
let Inst{22} = read;
|
|
let Inst{21-20} = 0b01;
|
|
}
|
|
|
|
def r : AXI<(outs), (ins addrmode2:$addr), MiscFrm, NoItinerary,
|
|
!strconcat(opc, "\t$addr"), []> {
|
|
let Inst{31-26} = 0b111101;
|
|
let Inst{25} = 1; // 1 for register form
|
|
let Inst{24} = data;
|
|
let Inst{22} = read;
|
|
let Inst{21-20} = 0b01;
|
|
let Inst{4} = 0;
|
|
}
|
|
}
|
|
|
|
defm PLD : APreLoad<1, 1, "pld">;
|
|
defm PLDW : APreLoad<1, 0, "pldw">;
|
|
defm PLI : APreLoad<0, 1, "pli">;
|
|
|
|
def SETENDBE : AXI<(outs),(ins), MiscFrm, NoItinerary, "setend\tbe",
|
|
[/* For disassembly only; pattern left blank */]>,
|
|
Requires<[IsARM]> {
|
|
let Inst{31-28} = 0b1111;
|
|
let Inst{27-20} = 0b00010000;
|
|
let Inst{16} = 1;
|
|
let Inst{9} = 1;
|
|
let Inst{7-4} = 0b0000;
|
|
}
|
|
|
|
def SETENDLE : AXI<(outs),(ins), MiscFrm, NoItinerary, "setend\tle",
|
|
[/* For disassembly only; pattern left blank */]>,
|
|
Requires<[IsARM]> {
|
|
let Inst{31-28} = 0b1111;
|
|
let Inst{27-20} = 0b00010000;
|
|
let Inst{16} = 1;
|
|
let Inst{9} = 0;
|
|
let Inst{7-4} = 0b0000;
|
|
}
|
|
|
|
def DBG : AI<(outs), (ins i32imm:$opt), MiscFrm, NoItinerary, "dbg", "\t$opt",
|
|
[/* For disassembly only; pattern left blank */]>,
|
|
Requires<[IsARM, HasV7]> {
|
|
let Inst{27-16} = 0b001100100000;
|
|
let Inst{7-4} = 0b1111;
|
|
}
|
|
|
|
// A5.4 Permanently UNDEFINED instructions.
|
|
def TRAP : AI<(outs), (ins), MiscFrm, NoItinerary, "trap", "",
|
|
[/* For disassembly only; pattern left blank */]>,
|
|
Requires<[IsARM]> {
|
|
let Inst{27-25} = 0b011;
|
|
let Inst{24-20} = 0b11111;
|
|
let Inst{7-5} = 0b111;
|
|
let Inst{4} = 0b1;
|
|
}
|
|
|
|
// Address computation and loads and stores in PIC mode.
|
|
let isNotDuplicable = 1 in {
|
|
def PICADD : AXI1<0b0100, (outs GPR:$dst), (ins GPR:$a, pclabel:$cp, pred:$p),
|
|
Pseudo, IIC_iALUr, "\n$cp:\n\tadd$p\t$dst, pc, $a",
|
|
[(set GPR:$dst, (ARMpic_add GPR:$a, imm:$cp))]>;
|
|
|
|
let AddedComplexity = 10 in {
|
|
def PICLDR : AXI2ldw<(outs GPR:$dst), (ins addrmodepc:$addr, pred:$p),
|
|
Pseudo, IIC_iLoadr, "\n${addr:label}:\n\tldr$p\t$dst, $addr",
|
|
[(set GPR:$dst, (load addrmodepc:$addr))]>;
|
|
|
|
def PICLDRH : AXI3ldh<(outs GPR:$dst), (ins addrmodepc:$addr, pred:$p),
|
|
Pseudo, IIC_iLoadr, "\n${addr:label}:\n\tldrh${p}\t$dst, $addr",
|
|
[(set GPR:$dst, (zextloadi16 addrmodepc:$addr))]>;
|
|
|
|
def PICLDRB : AXI2ldb<(outs GPR:$dst), (ins addrmodepc:$addr, pred:$p),
|
|
Pseudo, IIC_iLoadr, "\n${addr:label}:\n\tldrb${p}\t$dst, $addr",
|
|
[(set GPR:$dst, (zextloadi8 addrmodepc:$addr))]>;
|
|
|
|
def PICLDRSH : AXI3ldsh<(outs GPR:$dst), (ins addrmodepc:$addr, pred:$p),
|
|
Pseudo, IIC_iLoadr, "\n${addr:label}:\n\tldrsh${p}\t$dst, $addr",
|
|
[(set GPR:$dst, (sextloadi16 addrmodepc:$addr))]>;
|
|
|
|
def PICLDRSB : AXI3ldsb<(outs GPR:$dst), (ins addrmodepc:$addr, pred:$p),
|
|
Pseudo, IIC_iLoadr, "\n${addr:label}:\n\tldrsb${p}\t$dst, $addr",
|
|
[(set GPR:$dst, (sextloadi8 addrmodepc:$addr))]>;
|
|
}
|
|
let AddedComplexity = 10 in {
|
|
def PICSTR : AXI2stw<(outs), (ins GPR:$src, addrmodepc:$addr, pred:$p),
|
|
Pseudo, IIC_iStorer, "\n${addr:label}:\n\tstr$p\t$src, $addr",
|
|
[(store GPR:$src, addrmodepc:$addr)]>;
|
|
|
|
def PICSTRH : AXI3sth<(outs), (ins GPR:$src, addrmodepc:$addr, pred:$p),
|
|
Pseudo, IIC_iStorer, "\n${addr:label}:\n\tstrh${p}\t$src, $addr",
|
|
[(truncstorei16 GPR:$src, addrmodepc:$addr)]>;
|
|
|
|
def PICSTRB : AXI2stb<(outs), (ins GPR:$src, addrmodepc:$addr, pred:$p),
|
|
Pseudo, IIC_iStorer, "\n${addr:label}:\n\tstrb${p}\t$src, $addr",
|
|
[(truncstorei8 GPR:$src, addrmodepc:$addr)]>;
|
|
}
|
|
} // isNotDuplicable = 1
|
|
|
|
|
|
// LEApcrel - Load a pc-relative address into a register without offending the
|
|
// assembler.
|
|
def LEApcrel : AXI1<0x0, (outs GPR:$dst), (ins i32imm:$label, pred:$p),
|
|
Pseudo, IIC_iALUi,
|
|
!strconcat(!strconcat(".set ${:private}PCRELV${:uid}, ($label-(",
|
|
"${:private}PCRELL${:uid}+8))\n"),
|
|
!strconcat("${:private}PCRELL${:uid}:\n\t",
|
|
"add$p\t$dst, pc, #${:private}PCRELV${:uid}")),
|
|
[]>;
|
|
|
|
def LEApcrelJT : AXI1<0x0, (outs GPR:$dst),
|
|
(ins i32imm:$label, nohash_imm:$id, pred:$p),
|
|
Pseudo, IIC_iALUi,
|
|
!strconcat(!strconcat(".set ${:private}PCRELV${:uid}, "
|
|
"(${label}_${id}-(",
|
|
"${:private}PCRELL${:uid}+8))\n"),
|
|
!strconcat("${:private}PCRELL${:uid}:\n\t",
|
|
"add$p\t$dst, pc, #${:private}PCRELV${:uid}")),
|
|
[]> {
|
|
let Inst{25} = 1;
|
|
}
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// Control Flow Instructions.
|
|
//
|
|
|
|
let isReturn = 1, isTerminator = 1, isBarrier = 1 in {
|
|
// ARMV4T and above
|
|
def BX_RET : AI<(outs), (ins), BrMiscFrm, IIC_Br,
|
|
"bx", "\tlr", [(ARMretflag)]>,
|
|
Requires<[IsARM, HasV4T]> {
|
|
let Inst{3-0} = 0b1110;
|
|
let Inst{7-4} = 0b0001;
|
|
let Inst{19-8} = 0b111111111111;
|
|
let Inst{27-20} = 0b00010010;
|
|
}
|
|
|
|
// ARMV4 only
|
|
def MOVPCLR : AI<(outs), (ins), BrMiscFrm, IIC_Br,
|
|
"mov", "\tpc, lr", [(ARMretflag)]>,
|
|
Requires<[IsARM, NoV4T]> {
|
|
let Inst{11-0} = 0b000000001110;
|
|
let Inst{15-12} = 0b1111;
|
|
let Inst{19-16} = 0b0000;
|
|
let Inst{27-20} = 0b00011010;
|
|
}
|
|
}
|
|
|
|
// Indirect branches
|
|
let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in {
|
|
// ARMV4T and above
|
|
def BRIND : AXI<(outs), (ins GPR:$dst), BrMiscFrm, IIC_Br, "bx\t$dst",
|
|
[(brind GPR:$dst)]>,
|
|
Requires<[IsARM, HasV4T]> {
|
|
let Inst{7-4} = 0b0001;
|
|
let Inst{19-8} = 0b111111111111;
|
|
let Inst{27-20} = 0b00010010;
|
|
let Inst{31-28} = 0b1110;
|
|
}
|
|
|
|
// ARMV4 only
|
|
def MOVPCRX : AXI<(outs), (ins GPR:$dst), BrMiscFrm, IIC_Br, "mov\tpc, $dst",
|
|
[(brind GPR:$dst)]>,
|
|
Requires<[IsARM, NoV4T]> {
|
|
let Inst{11-4} = 0b00000000;
|
|
let Inst{15-12} = 0b1111;
|
|
let Inst{19-16} = 0b0000;
|
|
let Inst{27-20} = 0b00011010;
|
|
let Inst{31-28} = 0b1110;
|
|
}
|
|
}
|
|
|
|
// FIXME: remove when we have a way to marking a MI with these properties.
|
|
// FIXME: Should pc be an implicit operand like PICADD, etc?
|
|
let isReturn = 1, isTerminator = 1, isBarrier = 1, mayLoad = 1,
|
|
hasExtraDefRegAllocReq = 1 in
|
|
def LDM_RET : AXI4ld<(outs GPR:$wb), (ins addrmode4:$addr, pred:$p,
|
|
reglist:$dsts, variable_ops),
|
|
LdStMulFrm, IIC_Br,
|
|
"ldm${addr:submode}${p}\t$addr, $dsts",
|
|
"$addr.addr = $wb", []>;
|
|
|
|
// On non-Darwin platforms R9 is callee-saved.
|
|
let isCall = 1,
|
|
Defs = [R0, R1, R2, R3, R12, LR,
|
|
D0, D1, D2, D3, D4, D5, D6, D7,
|
|
D16, D17, D18, D19, D20, D21, D22, D23,
|
|
D24, D25, D26, D27, D28, D29, D30, D31, CPSR, FPSCR] in {
|
|
def BL : ABXI<0b1011, (outs), (ins i32imm:$func, variable_ops),
|
|
IIC_Br, "bl\t${func:call}",
|
|
[(ARMcall tglobaladdr:$func)]>,
|
|
Requires<[IsARM, IsNotDarwin]> {
|
|
let Inst{31-28} = 0b1110;
|
|
}
|
|
|
|
def BL_pred : ABI<0b1011, (outs), (ins i32imm:$func, variable_ops),
|
|
IIC_Br, "bl", "\t${func:call}",
|
|
[(ARMcall_pred tglobaladdr:$func)]>,
|
|
Requires<[IsARM, IsNotDarwin]>;
|
|
|
|
// ARMv5T and above
|
|
def BLX : AXI<(outs), (ins GPR:$func, variable_ops), BrMiscFrm,
|
|
IIC_Br, "blx\t$func",
|
|
[(ARMcall GPR:$func)]>,
|
|
Requires<[IsARM, HasV5T, IsNotDarwin]> {
|
|
let Inst{7-4} = 0b0011;
|
|
let Inst{19-8} = 0b111111111111;
|
|
let Inst{27-20} = 0b00010010;
|
|
}
|
|
|
|
// ARMv4T
|
|
// Note: Restrict $func to the tGPR regclass to prevent it being in LR.
|
|
def BX : ABXIx2<(outs), (ins tGPR:$func, variable_ops),
|
|
IIC_Br, "mov\tlr, pc\n\tbx\t$func",
|
|
[(ARMcall_nolink tGPR:$func)]>,
|
|
Requires<[IsARM, HasV4T, IsNotDarwin]> {
|
|
let Inst{7-4} = 0b0001;
|
|
let Inst{19-8} = 0b111111111111;
|
|
let Inst{27-20} = 0b00010010;
|
|
}
|
|
|
|
// ARMv4
|
|
def BMOVPCRX : ABXIx2<(outs), (ins tGPR:$func, variable_ops),
|
|
IIC_Br, "mov\tlr, pc\n\tmov\tpc, $func",
|
|
[(ARMcall_nolink tGPR:$func)]>,
|
|
Requires<[IsARM, NoV4T, IsNotDarwin]> {
|
|
let Inst{11-4} = 0b00000000;
|
|
let Inst{15-12} = 0b1111;
|
|
let Inst{19-16} = 0b0000;
|
|
let Inst{27-20} = 0b00011010;
|
|
}
|
|
}
|
|
|
|
// On Darwin R9 is call-clobbered.
|
|
let isCall = 1,
|
|
Defs = [R0, R1, R2, R3, R9, R12, LR,
|
|
D0, D1, D2, D3, D4, D5, D6, D7,
|
|
D16, D17, D18, D19, D20, D21, D22, D23,
|
|
D24, D25, D26, D27, D28, D29, D30, D31, CPSR, FPSCR] in {
|
|
def BLr9 : ABXI<0b1011, (outs), (ins i32imm:$func, variable_ops),
|
|
IIC_Br, "bl\t${func:call}",
|
|
[(ARMcall tglobaladdr:$func)]>, Requires<[IsARM, IsDarwin]> {
|
|
let Inst{31-28} = 0b1110;
|
|
}
|
|
|
|
def BLr9_pred : ABI<0b1011, (outs), (ins i32imm:$func, variable_ops),
|
|
IIC_Br, "bl", "\t${func:call}",
|
|
[(ARMcall_pred tglobaladdr:$func)]>,
|
|
Requires<[IsARM, IsDarwin]>;
|
|
|
|
// ARMv5T and above
|
|
def BLXr9 : AXI<(outs), (ins GPR:$func, variable_ops), BrMiscFrm,
|
|
IIC_Br, "blx\t$func",
|
|
[(ARMcall GPR:$func)]>, Requires<[IsARM, HasV5T, IsDarwin]> {
|
|
let Inst{7-4} = 0b0011;
|
|
let Inst{19-8} = 0b111111111111;
|
|
let Inst{27-20} = 0b00010010;
|
|
}
|
|
|
|
// ARMv4T
|
|
// Note: Restrict $func to the tGPR regclass to prevent it being in LR.
|
|
def BXr9 : ABXIx2<(outs), (ins tGPR:$func, variable_ops),
|
|
IIC_Br, "mov\tlr, pc\n\tbx\t$func",
|
|
[(ARMcall_nolink tGPR:$func)]>,
|
|
Requires<[IsARM, HasV4T, IsDarwin]> {
|
|
let Inst{7-4} = 0b0001;
|
|
let Inst{19-8} = 0b111111111111;
|
|
let Inst{27-20} = 0b00010010;
|
|
}
|
|
|
|
// ARMv4
|
|
def BMOVPCRXr9 : ABXIx2<(outs), (ins tGPR:$func, variable_ops),
|
|
IIC_Br, "mov\tlr, pc\n\tmov\tpc, $func",
|
|
[(ARMcall_nolink tGPR:$func)]>,
|
|
Requires<[IsARM, NoV4T, IsDarwin]> {
|
|
let Inst{11-4} = 0b00000000;
|
|
let Inst{15-12} = 0b1111;
|
|
let Inst{19-16} = 0b0000;
|
|
let Inst{27-20} = 0b00011010;
|
|
}
|
|
}
|
|
|
|
let isBranch = 1, isTerminator = 1 in {
|
|
// B is "predicable" since it can be xformed into a Bcc.
|
|
let isBarrier = 1 in {
|
|
let isPredicable = 1 in
|
|
def B : ABXI<0b1010, (outs), (ins brtarget:$target), IIC_Br,
|
|
"b\t$target", [(br bb:$target)]>;
|
|
|
|
let isNotDuplicable = 1, isIndirectBranch = 1 in {
|
|
def BR_JTr : JTI<(outs), (ins GPR:$target, jtblock_operand:$jt, i32imm:$id),
|
|
IIC_Br, "mov\tpc, $target \n$jt",
|
|
[(ARMbrjt GPR:$target, tjumptable:$jt, imm:$id)]> {
|
|
let Inst{11-4} = 0b00000000;
|
|
let Inst{15-12} = 0b1111;
|
|
let Inst{20} = 0; // S Bit
|
|
let Inst{24-21} = 0b1101;
|
|
let Inst{27-25} = 0b000;
|
|
}
|
|
def BR_JTm : JTI<(outs),
|
|
(ins addrmode2:$target, jtblock_operand:$jt, i32imm:$id),
|
|
IIC_Br, "ldr\tpc, $target \n$jt",
|
|
[(ARMbrjt (i32 (load addrmode2:$target)), tjumptable:$jt,
|
|
imm:$id)]> {
|
|
let Inst{15-12} = 0b1111;
|
|
let Inst{20} = 1; // L bit
|
|
let Inst{21} = 0; // W bit
|
|
let Inst{22} = 0; // B bit
|
|
let Inst{24} = 1; // P bit
|
|
let Inst{27-25} = 0b011;
|
|
}
|
|
def BR_JTadd : JTI<(outs),
|
|
(ins GPR:$target, GPR:$idx, jtblock_operand:$jt, i32imm:$id),
|
|
IIC_Br, "add\tpc, $target, $idx \n$jt",
|
|
[(ARMbrjt (add GPR:$target, GPR:$idx), tjumptable:$jt,
|
|
imm:$id)]> {
|
|
let Inst{15-12} = 0b1111;
|
|
let Inst{20} = 0; // S bit
|
|
let Inst{24-21} = 0b0100;
|
|
let Inst{27-25} = 0b000;
|
|
}
|
|
} // isNotDuplicable = 1, isIndirectBranch = 1
|
|
} // isBarrier = 1
|
|
|
|
// FIXME: should be able to write a pattern for ARMBrcond, but can't use
|
|
// a two-value operand where a dag node expects two operands. :(
|
|
def Bcc : ABI<0b1010, (outs), (ins brtarget:$target),
|
|
IIC_Br, "b", "\t$target",
|
|
[/*(ARMbrcond bb:$target, imm:$cc, CCR:$ccr)*/]>;
|
|
}
|
|
|
|
// Branch and Exchange Jazelle -- for disassembly only
|
|
def BXJ : ABI<0b0001, (outs), (ins GPR:$func), NoItinerary, "bxj", "\t$func",
|
|
[/* For disassembly only; pattern left blank */]> {
|
|
let Inst{23-20} = 0b0010;
|
|
//let Inst{19-8} = 0xfff;
|
|
let Inst{7-4} = 0b0010;
|
|
}
|
|
|
|
// Secure Monitor Call is a system instruction -- for disassembly only
|
|
def SMC : ABI<0b0001, (outs), (ins i32imm:$opt), NoItinerary, "smc", "\t$opt",
|
|
[/* For disassembly only; pattern left blank */]> {
|
|
let Inst{23-20} = 0b0110;
|
|
let Inst{7-4} = 0b0111;
|
|
}
|
|
|
|
// Supervisor Call (Software Interrupt) -- for disassembly only
|
|
let isCall = 1 in {
|
|
def SVC : ABI<0b1111, (outs), (ins i32imm:$svc), IIC_Br, "svc", "\t$svc",
|
|
[/* For disassembly only; pattern left blank */]>;
|
|
}
|
|
|
|
// Store Return State is a system instruction -- for disassembly only
|
|
def SRSW : ABXI<{1,0,0,?}, (outs), (ins addrmode4:$addr, i32imm:$mode),
|
|
NoItinerary, "srs${addr:submode}\tsp!, $mode",
|
|
[/* For disassembly only; pattern left blank */]> {
|
|
let Inst{31-28} = 0b1111;
|
|
let Inst{22-20} = 0b110; // W = 1
|
|
}
|
|
|
|
def SRS : ABXI<{1,0,0,?}, (outs), (ins addrmode4:$addr, i32imm:$mode),
|
|
NoItinerary, "srs${addr:submode}\tsp, $mode",
|
|
[/* For disassembly only; pattern left blank */]> {
|
|
let Inst{31-28} = 0b1111;
|
|
let Inst{22-20} = 0b100; // W = 0
|
|
}
|
|
|
|
// Return From Exception is a system instruction -- for disassembly only
|
|
def RFEW : ABXI<{1,0,0,?}, (outs), (ins addrmode4:$addr, GPR:$base),
|
|
NoItinerary, "rfe${addr:submode}\t$base!",
|
|
[/* For disassembly only; pattern left blank */]> {
|
|
let Inst{31-28} = 0b1111;
|
|
let Inst{22-20} = 0b011; // W = 1
|
|
}
|
|
|
|
def RFE : ABXI<{1,0,0,?}, (outs), (ins addrmode4:$addr, GPR:$base),
|
|
NoItinerary, "rfe${addr:submode}\t$base",
|
|
[/* For disassembly only; pattern left blank */]> {
|
|
let Inst{31-28} = 0b1111;
|
|
let Inst{22-20} = 0b001; // W = 0
|
|
}
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// Load / store Instructions.
|
|
//
|
|
|
|
// Load
|
|
let canFoldAsLoad = 1, isReMaterializable = 1 in
|
|
def LDR : AI2ldw<(outs GPR:$dst), (ins addrmode2:$addr), LdFrm, IIC_iLoadr,
|
|
"ldr", "\t$dst, $addr",
|
|
[(set GPR:$dst, (load addrmode2:$addr))]>;
|
|
|
|
// Special LDR for loads from non-pc-relative constpools.
|
|
let canFoldAsLoad = 1, mayLoad = 1, isReMaterializable = 1 in
|
|
def LDRcp : AI2ldw<(outs GPR:$dst), (ins addrmode2:$addr), LdFrm, IIC_iLoadr,
|
|
"ldr", "\t$dst, $addr", []>;
|
|
|
|
// Loads with zero extension
|
|
def LDRH : AI3ldh<(outs GPR:$dst), (ins addrmode3:$addr), LdMiscFrm,
|
|
IIC_iLoadr, "ldrh", "\t$dst, $addr",
|
|
[(set GPR:$dst, (zextloadi16 addrmode3:$addr))]>;
|
|
|
|
def LDRB : AI2ldb<(outs GPR:$dst), (ins addrmode2:$addr), LdFrm,
|
|
IIC_iLoadr, "ldrb", "\t$dst, $addr",
|
|
[(set GPR:$dst, (zextloadi8 addrmode2:$addr))]>;
|
|
|
|
// Loads with sign extension
|
|
def LDRSH : AI3ldsh<(outs GPR:$dst), (ins addrmode3:$addr), LdMiscFrm,
|
|
IIC_iLoadr, "ldrsh", "\t$dst, $addr",
|
|
[(set GPR:$dst, (sextloadi16 addrmode3:$addr))]>;
|
|
|
|
def LDRSB : AI3ldsb<(outs GPR:$dst), (ins addrmode3:$addr), LdMiscFrm,
|
|
IIC_iLoadr, "ldrsb", "\t$dst, $addr",
|
|
[(set GPR:$dst, (sextloadi8 addrmode3:$addr))]>;
|
|
|
|
let mayLoad = 1, hasExtraDefRegAllocReq = 1 in {
|
|
// Load doubleword
|
|
def LDRD : AI3ldd<(outs GPR:$dst1, GPR:$dst2), (ins addrmode3:$addr), LdMiscFrm,
|
|
IIC_iLoadr, "ldrd", "\t$dst1, $addr",
|
|
[]>, Requires<[IsARM, HasV5TE]>;
|
|
|
|
// Indexed loads
|
|
def LDR_PRE : AI2ldwpr<(outs GPR:$dst, GPR:$base_wb),
|
|
(ins addrmode2:$addr), LdFrm, IIC_iLoadru,
|
|
"ldr", "\t$dst, $addr!", "$addr.base = $base_wb", []>;
|
|
|
|
def LDR_POST : AI2ldwpo<(outs GPR:$dst, GPR:$base_wb),
|
|
(ins GPR:$base, am2offset:$offset), LdFrm, IIC_iLoadru,
|
|
"ldr", "\t$dst, [$base], $offset", "$base = $base_wb", []>;
|
|
|
|
def LDRH_PRE : AI3ldhpr<(outs GPR:$dst, GPR:$base_wb),
|
|
(ins addrmode3:$addr), LdMiscFrm, IIC_iLoadru,
|
|
"ldrh", "\t$dst, $addr!", "$addr.base = $base_wb", []>;
|
|
|
|
def LDRH_POST : AI3ldhpo<(outs GPR:$dst, GPR:$base_wb),
|
|
(ins GPR:$base,am3offset:$offset), LdMiscFrm, IIC_iLoadru,
|
|
"ldrh", "\t$dst, [$base], $offset", "$base = $base_wb", []>;
|
|
|
|
def LDRB_PRE : AI2ldbpr<(outs GPR:$dst, GPR:$base_wb),
|
|
(ins addrmode2:$addr), LdFrm, IIC_iLoadru,
|
|
"ldrb", "\t$dst, $addr!", "$addr.base = $base_wb", []>;
|
|
|
|
def LDRB_POST : AI2ldbpo<(outs GPR:$dst, GPR:$base_wb),
|
|
(ins GPR:$base,am2offset:$offset), LdFrm, IIC_iLoadru,
|
|
"ldrb", "\t$dst, [$base], $offset", "$base = $base_wb", []>;
|
|
|
|
def LDRSH_PRE : AI3ldshpr<(outs GPR:$dst, GPR:$base_wb),
|
|
(ins addrmode3:$addr), LdMiscFrm, IIC_iLoadru,
|
|
"ldrsh", "\t$dst, $addr!", "$addr.base = $base_wb", []>;
|
|
|
|
def LDRSH_POST: AI3ldshpo<(outs GPR:$dst, GPR:$base_wb),
|
|
(ins GPR:$base,am3offset:$offset), LdMiscFrm, IIC_iLoadru,
|
|
"ldrsh", "\t$dst, [$base], $offset", "$base = $base_wb", []>;
|
|
|
|
def LDRSB_PRE : AI3ldsbpr<(outs GPR:$dst, GPR:$base_wb),
|
|
(ins addrmode3:$addr), LdMiscFrm, IIC_iLoadru,
|
|
"ldrsb", "\t$dst, $addr!", "$addr.base = $base_wb", []>;
|
|
|
|
def LDRSB_POST: AI3ldsbpo<(outs GPR:$dst, GPR:$base_wb),
|
|
(ins GPR:$base,am3offset:$offset), LdMiscFrm, IIC_iLoadru,
|
|
"ldrsb", "\t$dst, [$base], $offset", "$base = $base_wb", []>;
|
|
|
|
// For disassembly only
|
|
def LDRD_PRE : AI3lddpr<(outs GPR:$dst1, GPR:$dst2, GPR:$base_wb),
|
|
(ins addrmode3:$addr), LdMiscFrm, IIC_iLoadr,
|
|
"ldrd", "\t$dst1, $dst2, $addr!", "$addr.base = $base_wb", []>,
|
|
Requires<[IsARM, HasV5TE]>;
|
|
|
|
// For disassembly only
|
|
def LDRD_POST : AI3lddpo<(outs GPR:$dst1, GPR:$dst2, GPR:$base_wb),
|
|
(ins GPR:$base,am3offset:$offset), LdMiscFrm, IIC_iLoadr,
|
|
"ldrd", "\t$dst1, $dst2, [$base], $offset", "$base = $base_wb", []>,
|
|
Requires<[IsARM, HasV5TE]>;
|
|
|
|
}
|
|
|
|
// LDRT, LDRBT, LDRSBT, LDRHT, LDRSHT are for disassembly only.
|
|
|
|
def LDRT : AI2ldwpo<(outs GPR:$dst, GPR:$base_wb),
|
|
(ins GPR:$base, am2offset:$offset), LdFrm, IIC_iLoadru,
|
|
"ldrt", "\t$dst, [$base], $offset", "$base = $base_wb", []> {
|
|
let Inst{21} = 1; // overwrite
|
|
}
|
|
|
|
def LDRBT : AI2ldbpo<(outs GPR:$dst, GPR:$base_wb),
|
|
(ins GPR:$base,am2offset:$offset), LdFrm, IIC_iLoadru,
|
|
"ldrbt", "\t$dst, [$base], $offset", "$base = $base_wb", []> {
|
|
let Inst{21} = 1; // overwrite
|
|
}
|
|
|
|
def LDRSBT : AI3ldsbpo<(outs GPR:$dst, GPR:$base_wb),
|
|
(ins GPR:$base,am2offset:$offset), LdMiscFrm, IIC_iLoadru,
|
|
"ldrsbt", "\t$dst, [$base], $offset", "$base = $base_wb", []> {
|
|
let Inst{21} = 1; // overwrite
|
|
}
|
|
|
|
def LDRHT : AI3ldhpo<(outs GPR:$dst, GPR:$base_wb),
|
|
(ins GPR:$base, am3offset:$offset), LdMiscFrm, IIC_iLoadru,
|
|
"ldrht", "\t$dst, [$base], $offset", "$base = $base_wb", []> {
|
|
let Inst{21} = 1; // overwrite
|
|
}
|
|
|
|
def LDRSHT : AI3ldshpo<(outs GPR:$dst, GPR:$base_wb),
|
|
(ins GPR:$base,am3offset:$offset), LdMiscFrm, IIC_iLoadru,
|
|
"ldrsht", "\t$dst, [$base], $offset", "$base = $base_wb", []> {
|
|
let Inst{21} = 1; // overwrite
|
|
}
|
|
|
|
// Store
|
|
def STR : AI2stw<(outs), (ins GPR:$src, addrmode2:$addr), StFrm, IIC_iStorer,
|
|
"str", "\t$src, $addr",
|
|
[(store GPR:$src, addrmode2:$addr)]>;
|
|
|
|
// Stores with truncate
|
|
def STRH : AI3sth<(outs), (ins GPR:$src, addrmode3:$addr), StMiscFrm,
|
|
IIC_iStorer, "strh", "\t$src, $addr",
|
|
[(truncstorei16 GPR:$src, addrmode3:$addr)]>;
|
|
|
|
def STRB : AI2stb<(outs), (ins GPR:$src, addrmode2:$addr), StFrm, IIC_iStorer,
|
|
"strb", "\t$src, $addr",
|
|
[(truncstorei8 GPR:$src, addrmode2:$addr)]>;
|
|
|
|
// Store doubleword
|
|
let mayStore = 1, hasExtraSrcRegAllocReq = 1 in
|
|
def STRD : AI3std<(outs), (ins GPR:$src1, GPR:$src2, addrmode3:$addr),
|
|
StMiscFrm, IIC_iStorer,
|
|
"strd", "\t$src1, $addr", []>, Requires<[IsARM, HasV5TE]>;
|
|
|
|
// Indexed stores
|
|
def STR_PRE : AI2stwpr<(outs GPR:$base_wb),
|
|
(ins GPR:$src, GPR:$base, am2offset:$offset),
|
|
StFrm, IIC_iStoreru,
|
|
"str", "\t$src, [$base, $offset]!", "$base = $base_wb",
|
|
[(set GPR:$base_wb,
|
|
(pre_store GPR:$src, GPR:$base, am2offset:$offset))]>;
|
|
|
|
def STR_POST : AI2stwpo<(outs GPR:$base_wb),
|
|
(ins GPR:$src, GPR:$base,am2offset:$offset),
|
|
StFrm, IIC_iStoreru,
|
|
"str", "\t$src, [$base], $offset", "$base = $base_wb",
|
|
[(set GPR:$base_wb,
|
|
(post_store GPR:$src, GPR:$base, am2offset:$offset))]>;
|
|
|
|
def STRH_PRE : AI3sthpr<(outs GPR:$base_wb),
|
|
(ins GPR:$src, GPR:$base,am3offset:$offset),
|
|
StMiscFrm, IIC_iStoreru,
|
|
"strh", "\t$src, [$base, $offset]!", "$base = $base_wb",
|
|
[(set GPR:$base_wb,
|
|
(pre_truncsti16 GPR:$src, GPR:$base,am3offset:$offset))]>;
|
|
|
|
def STRH_POST: AI3sthpo<(outs GPR:$base_wb),
|
|
(ins GPR:$src, GPR:$base,am3offset:$offset),
|
|
StMiscFrm, IIC_iStoreru,
|
|
"strh", "\t$src, [$base], $offset", "$base = $base_wb",
|
|
[(set GPR:$base_wb, (post_truncsti16 GPR:$src,
|
|
GPR:$base, am3offset:$offset))]>;
|
|
|
|
def STRB_PRE : AI2stbpr<(outs GPR:$base_wb),
|
|
(ins GPR:$src, GPR:$base,am2offset:$offset),
|
|
StFrm, IIC_iStoreru,
|
|
"strb", "\t$src, [$base, $offset]!", "$base = $base_wb",
|
|
[(set GPR:$base_wb, (pre_truncsti8 GPR:$src,
|
|
GPR:$base, am2offset:$offset))]>;
|
|
|
|
def STRB_POST: AI2stbpo<(outs GPR:$base_wb),
|
|
(ins GPR:$src, GPR:$base,am2offset:$offset),
|
|
StFrm, IIC_iStoreru,
|
|
"strb", "\t$src, [$base], $offset", "$base = $base_wb",
|
|
[(set GPR:$base_wb, (post_truncsti8 GPR:$src,
|
|
GPR:$base, am2offset:$offset))]>;
|
|
|
|
// For disassembly only
|
|
def STRD_PRE : AI3stdpr<(outs GPR:$base_wb),
|
|
(ins GPR:$src1, GPR:$src2, GPR:$base, am3offset:$offset),
|
|
StMiscFrm, IIC_iStoreru,
|
|
"strd", "\t$src1, $src2, [$base, $offset]!",
|
|
"$base = $base_wb", []>;
|
|
|
|
// For disassembly only
|
|
def STRD_POST: AI3stdpo<(outs GPR:$base_wb),
|
|
(ins GPR:$src1, GPR:$src2, GPR:$base, am3offset:$offset),
|
|
StMiscFrm, IIC_iStoreru,
|
|
"strd", "\t$src1, $src2, [$base], $offset",
|
|
"$base = $base_wb", []>;
|
|
|
|
// STRT, STRBT, and STRHT are for disassembly only.
|
|
|
|
def STRT : AI2stwpo<(outs GPR:$base_wb),
|
|
(ins GPR:$src, GPR:$base,am2offset:$offset),
|
|
StFrm, IIC_iStoreru,
|
|
"strt", "\t$src, [$base], $offset", "$base = $base_wb",
|
|
[/* For disassembly only; pattern left blank */]> {
|
|
let Inst{21} = 1; // overwrite
|
|
}
|
|
|
|
def STRBT : AI2stbpo<(outs GPR:$base_wb),
|
|
(ins GPR:$src, GPR:$base,am2offset:$offset),
|
|
StFrm, IIC_iStoreru,
|
|
"strbt", "\t$src, [$base], $offset", "$base = $base_wb",
|
|
[/* For disassembly only; pattern left blank */]> {
|
|
let Inst{21} = 1; // overwrite
|
|
}
|
|
|
|
def STRHT: AI3sthpo<(outs GPR:$base_wb),
|
|
(ins GPR:$src, GPR:$base,am3offset:$offset),
|
|
StMiscFrm, IIC_iStoreru,
|
|
"strht", "\t$src, [$base], $offset", "$base = $base_wb",
|
|
[/* For disassembly only; pattern left blank */]> {
|
|
let Inst{21} = 1; // overwrite
|
|
}
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// Load / store multiple Instructions.
|
|
//
|
|
|
|
let mayLoad = 1, hasExtraDefRegAllocReq = 1 in {
|
|
def LDM : AXI4ld<(outs), (ins addrmode4:$addr, pred:$p,
|
|
reglist:$dsts, variable_ops), LdStMulFrm, IIC_iLoadm,
|
|
"ldm${addr:submode}${p}\t$addr, $dsts", "", []>;
|
|
|
|
def LDM_UPD : AXI4ld<(outs GPR:$wb), (ins addrmode4:$addr, pred:$p,
|
|
reglist:$dsts, variable_ops),
|
|
LdStMulFrm, IIC_iLoadm,
|
|
"ldm${addr:submode}${p}\t$addr, $dsts",
|
|
"$addr.addr = $wb", []>;
|
|
} // mayLoad, hasExtraDefRegAllocReq
|
|
|
|
let mayStore = 1, hasExtraSrcRegAllocReq = 1 in {
|
|
def STM : AXI4st<(outs), (ins addrmode4:$addr, pred:$p,
|
|
reglist:$srcs, variable_ops), LdStMulFrm, IIC_iStorem,
|
|
"stm${addr:submode}${p}\t$addr, $srcs", "", []>;
|
|
|
|
def STM_UPD : AXI4st<(outs GPR:$wb), (ins addrmode4:$addr, pred:$p,
|
|
reglist:$srcs, variable_ops),
|
|
LdStMulFrm, IIC_iStorem,
|
|
"stm${addr:submode}${p}\t$addr, $srcs",
|
|
"$addr.addr = $wb", []>;
|
|
} // mayStore, hasExtraSrcRegAllocReq
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// Move Instructions.
|
|
//
|
|
|
|
let neverHasSideEffects = 1 in
|
|
def MOVr : AsI1<0b1101, (outs GPR:$dst), (ins GPR:$src), DPFrm, IIC_iMOVr,
|
|
"mov", "\t$dst, $src", []>, UnaryDP {
|
|
let Inst{11-4} = 0b00000000;
|
|
let Inst{25} = 0;
|
|
}
|
|
|
|
def MOVs : AsI1<0b1101, (outs GPR:$dst), (ins so_reg:$src),
|
|
DPSoRegFrm, IIC_iMOVsr,
|
|
"mov", "\t$dst, $src", [(set GPR:$dst, so_reg:$src)]>, UnaryDP {
|
|
let Inst{25} = 0;
|
|
}
|
|
|
|
let isReMaterializable = 1, isAsCheapAsAMove = 1 in
|
|
def MOVi : AsI1<0b1101, (outs GPR:$dst), (ins so_imm:$src), DPFrm, IIC_iMOVi,
|
|
"mov", "\t$dst, $src", [(set GPR:$dst, so_imm:$src)]>, UnaryDP {
|
|
let Inst{25} = 1;
|
|
}
|
|
|
|
let isReMaterializable = 1, isAsCheapAsAMove = 1 in
|
|
def MOVi16 : AI1<0b1000, (outs GPR:$dst), (ins i32imm:$src),
|
|
DPFrm, IIC_iMOVi,
|
|
"movw", "\t$dst, $src",
|
|
[(set GPR:$dst, imm0_65535:$src)]>,
|
|
Requires<[IsARM, HasV6T2]>, UnaryDP {
|
|
let Inst{20} = 0;
|
|
let Inst{25} = 1;
|
|
}
|
|
|
|
let Constraints = "$src = $dst" in
|
|
def MOVTi16 : AI1<0b1010, (outs GPR:$dst), (ins GPR:$src, i32imm:$imm),
|
|
DPFrm, IIC_iMOVi,
|
|
"movt", "\t$dst, $imm",
|
|
[(set GPR:$dst,
|
|
(or (and GPR:$src, 0xffff),
|
|
lo16AllZero:$imm))]>, UnaryDP,
|
|
Requires<[IsARM, HasV6T2]> {
|
|
let Inst{20} = 0;
|
|
let Inst{25} = 1;
|
|
}
|
|
|
|
def : ARMPat<(or GPR:$src, 0xffff0000), (MOVTi16 GPR:$src, 0xffff)>,
|
|
Requires<[IsARM, HasV6T2]>;
|
|
|
|
let Uses = [CPSR] in
|
|
def MOVrx : AsI1<0b1101, (outs GPR:$dst), (ins GPR:$src), Pseudo, IIC_iMOVsi,
|
|
"mov", "\t$dst, $src, rrx",
|
|
[(set GPR:$dst, (ARMrrx GPR:$src))]>, UnaryDP;
|
|
|
|
// These aren't really mov instructions, but we have to define them this way
|
|
// due to flag operands.
|
|
|
|
let Defs = [CPSR] in {
|
|
def MOVsrl_flag : AI1<0b1101, (outs GPR:$dst), (ins GPR:$src), Pseudo,
|
|
IIC_iMOVsi, "movs", "\t$dst, $src, lsr #1",
|
|
[(set GPR:$dst, (ARMsrl_flag GPR:$src))]>, UnaryDP;
|
|
def MOVsra_flag : AI1<0b1101, (outs GPR:$dst), (ins GPR:$src), Pseudo,
|
|
IIC_iMOVsi, "movs", "\t$dst, $src, asr #1",
|
|
[(set GPR:$dst, (ARMsra_flag GPR:$src))]>, UnaryDP;
|
|
}
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// Extend Instructions.
|
|
//
|
|
|
|
// Sign extenders
|
|
|
|
defm SXTB : AI_unary_rrot<0b01101010,
|
|
"sxtb", UnOpFrag<(sext_inreg node:$Src, i8)>>;
|
|
defm SXTH : AI_unary_rrot<0b01101011,
|
|
"sxth", UnOpFrag<(sext_inreg node:$Src, i16)>>;
|
|
|
|
defm SXTAB : AI_bin_rrot<0b01101010,
|
|
"sxtab", BinOpFrag<(add node:$LHS, (sext_inreg node:$RHS, i8))>>;
|
|
defm SXTAH : AI_bin_rrot<0b01101011,
|
|
"sxtah", BinOpFrag<(add node:$LHS, (sext_inreg node:$RHS,i16))>>;
|
|
|
|
// For disassembly only
|
|
defm SXTB16 : AI_unary_rrot_np<0b01101000, "sxtb16">;
|
|
|
|
// For disassembly only
|
|
defm SXTAB16 : AI_bin_rrot_np<0b01101000, "sxtab16">;
|
|
|
|
// Zero extenders
|
|
|
|
let AddedComplexity = 16 in {
|
|
defm UXTB : AI_unary_rrot<0b01101110,
|
|
"uxtb" , UnOpFrag<(and node:$Src, 0x000000FF)>>;
|
|
defm UXTH : AI_unary_rrot<0b01101111,
|
|
"uxth" , UnOpFrag<(and node:$Src, 0x0000FFFF)>>;
|
|
defm UXTB16 : AI_unary_rrot<0b01101100,
|
|
"uxtb16", UnOpFrag<(and node:$Src, 0x00FF00FF)>>;
|
|
|
|
def : ARMV6Pat<(and (shl GPR:$Src, (i32 8)), 0xFF00FF),
|
|
(UXTB16r_rot GPR:$Src, 24)>;
|
|
def : ARMV6Pat<(and (srl GPR:$Src, (i32 8)), 0xFF00FF),
|
|
(UXTB16r_rot GPR:$Src, 8)>;
|
|
|
|
defm UXTAB : AI_bin_rrot<0b01101110, "uxtab",
|
|
BinOpFrag<(add node:$LHS, (and node:$RHS, 0x00FF))>>;
|
|
defm UXTAH : AI_bin_rrot<0b01101111, "uxtah",
|
|
BinOpFrag<(add node:$LHS, (and node:$RHS, 0xFFFF))>>;
|
|
}
|
|
|
|
// This isn't safe in general, the add is two 16-bit units, not a 32-bit add.
|
|
// For disassembly only
|
|
defm UXTAB16 : AI_bin_rrot_np<0b01101100, "uxtab16">;
|
|
|
|
|
|
def SBFX : I<(outs GPR:$dst),
|
|
(ins GPR:$src, imm0_31:$lsb, imm0_31:$width),
|
|
AddrMode1, Size4Bytes, IndexModeNone, DPFrm, IIC_iALUi,
|
|
"sbfx", "\t$dst, $src, $lsb, $width", "", []>,
|
|
Requires<[IsARM, HasV6T2]> {
|
|
let Inst{27-21} = 0b0111101;
|
|
let Inst{6-4} = 0b101;
|
|
}
|
|
|
|
def UBFX : I<(outs GPR:$dst),
|
|
(ins GPR:$src, imm0_31:$lsb, imm0_31:$width),
|
|
AddrMode1, Size4Bytes, IndexModeNone, DPFrm, IIC_iALUi,
|
|
"ubfx", "\t$dst, $src, $lsb, $width", "", []>,
|
|
Requires<[IsARM, HasV6T2]> {
|
|
let Inst{27-21} = 0b0111111;
|
|
let Inst{6-4} = 0b101;
|
|
}
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// Arithmetic Instructions.
|
|
//
|
|
|
|
defm ADD : AsI1_bin_irs<0b0100, "add",
|
|
BinOpFrag<(add node:$LHS, node:$RHS)>, 1>;
|
|
defm SUB : AsI1_bin_irs<0b0010, "sub",
|
|
BinOpFrag<(sub node:$LHS, node:$RHS)>>;
|
|
|
|
// ADD and SUB with 's' bit set.
|
|
defm ADDS : AI1_bin_s_irs<0b0100, "adds",
|
|
BinOpFrag<(addc node:$LHS, node:$RHS)>, 1>;
|
|
defm SUBS : AI1_bin_s_irs<0b0010, "subs",
|
|
BinOpFrag<(subc node:$LHS, node:$RHS)>>;
|
|
|
|
defm ADC : AI1_adde_sube_irs<0b0101, "adc",
|
|
BinOpFrag<(adde_dead_carry node:$LHS, node:$RHS)>, 1>;
|
|
defm SBC : AI1_adde_sube_irs<0b0110, "sbc",
|
|
BinOpFrag<(sube_dead_carry node:$LHS, node:$RHS)>>;
|
|
defm ADCS : AI1_adde_sube_s_irs<0b0101, "adcs",
|
|
BinOpFrag<(adde_live_carry node:$LHS, node:$RHS)>, 1>;
|
|
defm SBCS : AI1_adde_sube_s_irs<0b0110, "sbcs",
|
|
BinOpFrag<(sube_live_carry node:$LHS, node:$RHS) >>;
|
|
|
|
// These don't define reg/reg forms, because they are handled above.
|
|
def RSBri : AsI1<0b0011, (outs GPR:$dst), (ins GPR:$a, so_imm:$b), DPFrm,
|
|
IIC_iALUi, "rsb", "\t$dst, $a, $b",
|
|
[(set GPR:$dst, (sub so_imm:$b, GPR:$a))]> {
|
|
let Inst{25} = 1;
|
|
}
|
|
|
|
def RSBrs : AsI1<0b0011, (outs GPR:$dst), (ins GPR:$a, so_reg:$b), DPSoRegFrm,
|
|
IIC_iALUsr, "rsb", "\t$dst, $a, $b",
|
|
[(set GPR:$dst, (sub so_reg:$b, GPR:$a))]> {
|
|
let Inst{25} = 0;
|
|
}
|
|
|
|
// RSB with 's' bit set.
|
|
let Defs = [CPSR] in {
|
|
def RSBSri : AI1<0b0011, (outs GPR:$dst), (ins GPR:$a, so_imm:$b), DPFrm,
|
|
IIC_iALUi, "rsbs", "\t$dst, $a, $b",
|
|
[(set GPR:$dst, (subc so_imm:$b, GPR:$a))]> {
|
|
let Inst{20} = 1;
|
|
let Inst{25} = 1;
|
|
}
|
|
def RSBSrs : AI1<0b0011, (outs GPR:$dst), (ins GPR:$a, so_reg:$b), DPSoRegFrm,
|
|
IIC_iALUsr, "rsbs", "\t$dst, $a, $b",
|
|
[(set GPR:$dst, (subc so_reg:$b, GPR:$a))]> {
|
|
let Inst{20} = 1;
|
|
let Inst{25} = 0;
|
|
}
|
|
}
|
|
|
|
let Uses = [CPSR] in {
|
|
def RSCri : AsI1<0b0111, (outs GPR:$dst), (ins GPR:$a, so_imm:$b),
|
|
DPFrm, IIC_iALUi, "rsc", "\t$dst, $a, $b",
|
|
[(set GPR:$dst, (sube_dead_carry so_imm:$b, GPR:$a))]>,
|
|
Requires<[IsARM]> {
|
|
let Inst{25} = 1;
|
|
}
|
|
def RSCrs : AsI1<0b0111, (outs GPR:$dst), (ins GPR:$a, so_reg:$b),
|
|
DPSoRegFrm, IIC_iALUsr, "rsc", "\t$dst, $a, $b",
|
|
[(set GPR:$dst, (sube_dead_carry so_reg:$b, GPR:$a))]>,
|
|
Requires<[IsARM]> {
|
|
let Inst{25} = 0;
|
|
}
|
|
}
|
|
|
|
// FIXME: Allow these to be predicated.
|
|
let Defs = [CPSR], Uses = [CPSR] in {
|
|
def RSCSri : AXI1<0b0111, (outs GPR:$dst), (ins GPR:$a, so_imm:$b),
|
|
DPFrm, IIC_iALUi, "rscs\t$dst, $a, $b",
|
|
[(set GPR:$dst, (sube_dead_carry so_imm:$b, GPR:$a))]>,
|
|
Requires<[IsARM]> {
|
|
let Inst{20} = 1;
|
|
let Inst{25} = 1;
|
|
}
|
|
def RSCSrs : AXI1<0b0111, (outs GPR:$dst), (ins GPR:$a, so_reg:$b),
|
|
DPSoRegFrm, IIC_iALUsr, "rscs\t$dst, $a, $b",
|
|
[(set GPR:$dst, (sube_dead_carry so_reg:$b, GPR:$a))]>,
|
|
Requires<[IsARM]> {
|
|
let Inst{20} = 1;
|
|
let Inst{25} = 0;
|
|
}
|
|
}
|
|
|
|
// (sub X, imm) gets canonicalized to (add X, -imm). Match this form.
|
|
def : ARMPat<(add GPR:$src, so_imm_neg:$imm),
|
|
(SUBri GPR:$src, so_imm_neg:$imm)>;
|
|
|
|
//def : ARMPat<(addc GPR:$src, so_imm_neg:$imm),
|
|
// (SUBSri GPR:$src, so_imm_neg:$imm)>;
|
|
//def : ARMPat<(adde GPR:$src, so_imm_neg:$imm),
|
|
// (SBCri GPR:$src, so_imm_neg:$imm)>;
|
|
|
|
// Note: These are implemented in C++ code, because they have to generate
|
|
// ADD/SUBrs instructions, which use a complex pattern that a xform function
|
|
// cannot produce.
|
|
// (mul X, 2^n+1) -> (add (X << n), X)
|
|
// (mul X, 2^n-1) -> (rsb X, (X << n))
|
|
|
|
// ARM Arithmetic Instruction -- for disassembly only
|
|
// GPR:$dst = GPR:$a op GPR:$b
|
|
class AAI<bits<8> op27_20, bits<4> op7_4, string opc>
|
|
: AI<(outs GPR:$dst), (ins GPR:$a, GPR:$b), DPFrm, IIC_iALUr,
|
|
opc, "\t$dst, $a, $b",
|
|
[/* For disassembly only; pattern left blank */]> {
|
|
let Inst{27-20} = op27_20;
|
|
let Inst{7-4} = op7_4;
|
|
}
|
|
|
|
// Saturating add/subtract -- for disassembly only
|
|
|
|
def QADD : AAI<0b00010000, 0b0101, "qadd">;
|
|
def QADD16 : AAI<0b01100010, 0b0001, "qadd16">;
|
|
def QADD8 : AAI<0b01100010, 0b1001, "qadd8">;
|
|
def QASX : AAI<0b01100010, 0b0011, "qasx">;
|
|
def QDADD : AAI<0b00010100, 0b0101, "qdadd">;
|
|
def QDSUB : AAI<0b00010110, 0b0101, "qdsub">;
|
|
def QSAX : AAI<0b01100010, 0b0101, "qsax">;
|
|
def QSUB : AAI<0b00010010, 0b0101, "qsub">;
|
|
def QSUB16 : AAI<0b01100010, 0b0111, "qsub16">;
|
|
def QSUB8 : AAI<0b01100010, 0b1111, "qsub8">;
|
|
def UQADD16 : AAI<0b01100110, 0b0001, "uqadd16">;
|
|
def UQADD8 : AAI<0b01100110, 0b1001, "uqadd8">;
|
|
def UQASX : AAI<0b01100110, 0b0011, "uqasx">;
|
|
def UQSAX : AAI<0b01100110, 0b0101, "uqsax">;
|
|
def UQSUB16 : AAI<0b01100110, 0b0111, "uqsub16">;
|
|
def UQSUB8 : AAI<0b01100110, 0b1111, "uqsub8">;
|
|
|
|
// Signed/Unsigned add/subtract -- for disassembly only
|
|
|
|
def SASX : AAI<0b01100001, 0b0011, "sasx">;
|
|
def SADD16 : AAI<0b01100001, 0b0001, "sadd16">;
|
|
def SADD8 : AAI<0b01100001, 0b1001, "sadd8">;
|
|
def SSAX : AAI<0b01100001, 0b0101, "ssax">;
|
|
def SSUB16 : AAI<0b01100001, 0b0111, "ssub16">;
|
|
def SSUB8 : AAI<0b01100001, 0b1111, "ssub8">;
|
|
def UASX : AAI<0b01100101, 0b0011, "uasx">;
|
|
def UADD16 : AAI<0b01100101, 0b0001, "uadd16">;
|
|
def UADD8 : AAI<0b01100101, 0b1001, "uadd8">;
|
|
def USAX : AAI<0b01100101, 0b0101, "usax">;
|
|
def USUB16 : AAI<0b01100101, 0b0111, "usub16">;
|
|
def USUB8 : AAI<0b01100101, 0b1111, "usub8">;
|
|
|
|
// Signed/Unsigned halving add/subtract -- for disassembly only
|
|
|
|
def SHASX : AAI<0b01100011, 0b0011, "shasx">;
|
|
def SHADD16 : AAI<0b01100011, 0b0001, "shadd16">;
|
|
def SHADD8 : AAI<0b01100011, 0b1001, "shadd8">;
|
|
def SHSAX : AAI<0b01100011, 0b0101, "shsax">;
|
|
def SHSUB16 : AAI<0b01100011, 0b0111, "shsub16">;
|
|
def SHSUB8 : AAI<0b01100011, 0b1111, "shsub8">;
|
|
def UHASX : AAI<0b01100111, 0b0011, "uhasx">;
|
|
def UHADD16 : AAI<0b01100111, 0b0001, "uhadd16">;
|
|
def UHADD8 : AAI<0b01100111, 0b1001, "uhadd8">;
|
|
def UHSAX : AAI<0b01100111, 0b0101, "uhsax">;
|
|
def UHSUB16 : AAI<0b01100111, 0b0111, "uhsub16">;
|
|
def UHSUB8 : AAI<0b01100111, 0b1111, "uhsub8">;
|
|
|
|
// Unsigned Sum of Absolute Differences [and Accumulate] -- for disassembly only
|
|
|
|
def USAD8 : AI<(outs GPR:$dst), (ins GPR:$a, GPR:$b),
|
|
MulFrm /* for convenience */, NoItinerary, "usad8",
|
|
"\t$dst, $a, $b", []>,
|
|
Requires<[IsARM, HasV6]> {
|
|
let Inst{27-20} = 0b01111000;
|
|
let Inst{15-12} = 0b1111;
|
|
let Inst{7-4} = 0b0001;
|
|
}
|
|
def USADA8 : AI<(outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc),
|
|
MulFrm /* for convenience */, NoItinerary, "usada8",
|
|
"\t$dst, $a, $b, $acc", []>,
|
|
Requires<[IsARM, HasV6]> {
|
|
let Inst{27-20} = 0b01111000;
|
|
let Inst{7-4} = 0b0001;
|
|
}
|
|
|
|
// Signed/Unsigned saturate -- for disassembly only
|
|
|
|
def SSATlsl : AI<(outs GPR:$dst), (ins i32imm:$bit_pos, GPR:$a, i32imm:$shamt),
|
|
DPFrm, NoItinerary, "ssat", "\t$dst, $bit_pos, $a, lsl $shamt",
|
|
[/* For disassembly only; pattern left blank */]> {
|
|
let Inst{27-21} = 0b0110101;
|
|
let Inst{6-4} = 0b001;
|
|
}
|
|
|
|
def SSATasr : AI<(outs GPR:$dst), (ins i32imm:$bit_pos, GPR:$a, i32imm:$shamt),
|
|
DPFrm, NoItinerary, "ssat", "\t$dst, $bit_pos, $a, asr $shamt",
|
|
[/* For disassembly only; pattern left blank */]> {
|
|
let Inst{27-21} = 0b0110101;
|
|
let Inst{6-4} = 0b101;
|
|
}
|
|
|
|
def SSAT16 : AI<(outs GPR:$dst), (ins i32imm:$bit_pos, GPR:$a), DPFrm,
|
|
NoItinerary, "ssat16", "\t$dst, $bit_pos, $a",
|
|
[/* For disassembly only; pattern left blank */]> {
|
|
let Inst{27-20} = 0b01101010;
|
|
let Inst{7-4} = 0b0011;
|
|
}
|
|
|
|
def USATlsl : AI<(outs GPR:$dst), (ins i32imm:$bit_pos, GPR:$a, i32imm:$shamt),
|
|
DPFrm, NoItinerary, "usat", "\t$dst, $bit_pos, $a, lsl $shamt",
|
|
[/* For disassembly only; pattern left blank */]> {
|
|
let Inst{27-21} = 0b0110111;
|
|
let Inst{6-4} = 0b001;
|
|
}
|
|
|
|
def USATasr : AI<(outs GPR:$dst), (ins i32imm:$bit_pos, GPR:$a, i32imm:$shamt),
|
|
DPFrm, NoItinerary, "usat", "\t$dst, $bit_pos, $a, asr $shamt",
|
|
[/* For disassembly only; pattern left blank */]> {
|
|
let Inst{27-21} = 0b0110111;
|
|
let Inst{6-4} = 0b101;
|
|
}
|
|
|
|
def USAT16 : AI<(outs GPR:$dst), (ins i32imm:$bit_pos, GPR:$a), DPFrm,
|
|
NoItinerary, "usat16", "\t$dst, $bit_pos, $a",
|
|
[/* For disassembly only; pattern left blank */]> {
|
|
let Inst{27-20} = 0b01101110;
|
|
let Inst{7-4} = 0b0011;
|
|
}
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// Bitwise Instructions.
|
|
//
|
|
|
|
defm AND : AsI1_bin_irs<0b0000, "and",
|
|
BinOpFrag<(and node:$LHS, node:$RHS)>, 1>;
|
|
defm ORR : AsI1_bin_irs<0b1100, "orr",
|
|
BinOpFrag<(or node:$LHS, node:$RHS)>, 1>;
|
|
defm EOR : AsI1_bin_irs<0b0001, "eor",
|
|
BinOpFrag<(xor node:$LHS, node:$RHS)>, 1>;
|
|
defm BIC : AsI1_bin_irs<0b1110, "bic",
|
|
BinOpFrag<(and node:$LHS, (not node:$RHS))>>;
|
|
|
|
def BFC : I<(outs GPR:$dst), (ins GPR:$src, bf_inv_mask_imm:$imm),
|
|
AddrMode1, Size4Bytes, IndexModeNone, DPFrm, IIC_iUNAsi,
|
|
"bfc", "\t$dst, $imm", "$src = $dst",
|
|
[(set GPR:$dst, (and GPR:$src, bf_inv_mask_imm:$imm))]>,
|
|
Requires<[IsARM, HasV6T2]> {
|
|
let Inst{27-21} = 0b0111110;
|
|
let Inst{6-0} = 0b0011111;
|
|
}
|
|
|
|
// A8.6.18 BFI - Bitfield insert (Encoding A1)
|
|
// Added for disassembler with the pattern field purposely left blank.
|
|
def BFI : I<(outs GPR:$dst), (ins GPR:$src, bf_inv_mask_imm:$imm),
|
|
AddrMode1, Size4Bytes, IndexModeNone, DPFrm, IIC_iUNAsi,
|
|
"bfi", "\t$dst, $src, $imm", "",
|
|
[/* For disassembly only; pattern left blank */]>,
|
|
Requires<[IsARM, HasV6T2]> {
|
|
let Inst{27-21} = 0b0111110;
|
|
let Inst{6-4} = 0b001; // Rn: Inst{3-0} != 15
|
|
}
|
|
|
|
def MVNr : AsI1<0b1111, (outs GPR:$dst), (ins GPR:$src), DPFrm, IIC_iMOVr,
|
|
"mvn", "\t$dst, $src",
|
|
[(set GPR:$dst, (not GPR:$src))]>, UnaryDP {
|
|
let Inst{25} = 0;
|
|
let Inst{11-4} = 0b00000000;
|
|
}
|
|
def MVNs : AsI1<0b1111, (outs GPR:$dst), (ins so_reg:$src), DPSoRegFrm,
|
|
IIC_iMOVsr, "mvn", "\t$dst, $src",
|
|
[(set GPR:$dst, (not so_reg:$src))]>, UnaryDP {
|
|
let Inst{25} = 0;
|
|
}
|
|
let isReMaterializable = 1, isAsCheapAsAMove = 1 in
|
|
def MVNi : AsI1<0b1111, (outs GPR:$dst), (ins so_imm:$imm), DPFrm,
|
|
IIC_iMOVi, "mvn", "\t$dst, $imm",
|
|
[(set GPR:$dst, so_imm_not:$imm)]>,UnaryDP {
|
|
let Inst{25} = 1;
|
|
}
|
|
|
|
def : ARMPat<(and GPR:$src, so_imm_not:$imm),
|
|
(BICri GPR:$src, so_imm_not:$imm)>;
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// Multiply Instructions.
|
|
//
|
|
|
|
let isCommutable = 1 in
|
|
def MUL : AsMul1I<0b0000000, (outs GPR:$dst), (ins GPR:$a, GPR:$b),
|
|
IIC_iMUL32, "mul", "\t$dst, $a, $b",
|
|
[(set GPR:$dst, (mul GPR:$a, GPR:$b))]>;
|
|
|
|
def MLA : AsMul1I<0b0000001, (outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$c),
|
|
IIC_iMAC32, "mla", "\t$dst, $a, $b, $c",
|
|
[(set GPR:$dst, (add (mul GPR:$a, GPR:$b), GPR:$c))]>;
|
|
|
|
def MLS : AMul1I<0b0000011, (outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$c),
|
|
IIC_iMAC32, "mls", "\t$dst, $a, $b, $c",
|
|
[(set GPR:$dst, (sub GPR:$c, (mul GPR:$a, GPR:$b)))]>,
|
|
Requires<[IsARM, HasV6T2]>;
|
|
|
|
// Extra precision multiplies with low / high results
|
|
let neverHasSideEffects = 1 in {
|
|
let isCommutable = 1 in {
|
|
def SMULL : AsMul1I<0b0000110, (outs GPR:$ldst, GPR:$hdst),
|
|
(ins GPR:$a, GPR:$b), IIC_iMUL64,
|
|
"smull", "\t$ldst, $hdst, $a, $b", []>;
|
|
|
|
def UMULL : AsMul1I<0b0000100, (outs GPR:$ldst, GPR:$hdst),
|
|
(ins GPR:$a, GPR:$b), IIC_iMUL64,
|
|
"umull", "\t$ldst, $hdst, $a, $b", []>;
|
|
}
|
|
|
|
// Multiply + accumulate
|
|
def SMLAL : AsMul1I<0b0000111, (outs GPR:$ldst, GPR:$hdst),
|
|
(ins GPR:$a, GPR:$b), IIC_iMAC64,
|
|
"smlal", "\t$ldst, $hdst, $a, $b", []>;
|
|
|
|
def UMLAL : AsMul1I<0b0000101, (outs GPR:$ldst, GPR:$hdst),
|
|
(ins GPR:$a, GPR:$b), IIC_iMAC64,
|
|
"umlal", "\t$ldst, $hdst, $a, $b", []>;
|
|
|
|
def UMAAL : AMul1I <0b0000010, (outs GPR:$ldst, GPR:$hdst),
|
|
(ins GPR:$a, GPR:$b), IIC_iMAC64,
|
|
"umaal", "\t$ldst, $hdst, $a, $b", []>,
|
|
Requires<[IsARM, HasV6]>;
|
|
} // neverHasSideEffects
|
|
|
|
// Most significant word multiply
|
|
def SMMUL : AMul2I <0b0111010, (outs GPR:$dst), (ins GPR:$a, GPR:$b),
|
|
IIC_iMUL32, "smmul", "\t$dst, $a, $b",
|
|
[(set GPR:$dst, (mulhs GPR:$a, GPR:$b))]>,
|
|
Requires<[IsARM, HasV6]> {
|
|
let Inst{7-4} = 0b0001;
|
|
let Inst{15-12} = 0b1111;
|
|
}
|
|
|
|
def SMMULR : AMul2I <0b0111010, (outs GPR:$dst), (ins GPR:$a, GPR:$b),
|
|
IIC_iMUL32, "smmulr", "\t$dst, $a, $b",
|
|
[/* For disassembly only; pattern left blank */]>,
|
|
Requires<[IsARM, HasV6]> {
|
|
let Inst{7-4} = 0b0011; // R = 1
|
|
let Inst{15-12} = 0b1111;
|
|
}
|
|
|
|
def SMMLA : AMul2I <0b0111010, (outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$c),
|
|
IIC_iMAC32, "smmla", "\t$dst, $a, $b, $c",
|
|
[(set GPR:$dst, (add (mulhs GPR:$a, GPR:$b), GPR:$c))]>,
|
|
Requires<[IsARM, HasV6]> {
|
|
let Inst{7-4} = 0b0001;
|
|
}
|
|
|
|
def SMMLAR : AMul2I <0b0111010, (outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$c),
|
|
IIC_iMAC32, "smmlar", "\t$dst, $a, $b, $c",
|
|
[/* For disassembly only; pattern left blank */]>,
|
|
Requires<[IsARM, HasV6]> {
|
|
let Inst{7-4} = 0b0011; // R = 1
|
|
}
|
|
|
|
def SMMLS : AMul2I <0b0111010, (outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$c),
|
|
IIC_iMAC32, "smmls", "\t$dst, $a, $b, $c",
|
|
[(set GPR:$dst, (sub GPR:$c, (mulhs GPR:$a, GPR:$b)))]>,
|
|
Requires<[IsARM, HasV6]> {
|
|
let Inst{7-4} = 0b1101;
|
|
}
|
|
|
|
def SMMLSR : AMul2I <0b0111010, (outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$c),
|
|
IIC_iMAC32, "smmlsr", "\t$dst, $a, $b, $c",
|
|
[/* For disassembly only; pattern left blank */]>,
|
|
Requires<[IsARM, HasV6]> {
|
|
let Inst{7-4} = 0b1111; // R = 1
|
|
}
|
|
|
|
multiclass AI_smul<string opc, PatFrag opnode> {
|
|
def BB : AMulxyI<0b0001011, (outs GPR:$dst), (ins GPR:$a, GPR:$b),
|
|
IIC_iMUL32, !strconcat(opc, "bb"), "\t$dst, $a, $b",
|
|
[(set GPR:$dst, (opnode (sext_inreg GPR:$a, i16),
|
|
(sext_inreg GPR:$b, i16)))]>,
|
|
Requires<[IsARM, HasV5TE]> {
|
|
let Inst{5} = 0;
|
|
let Inst{6} = 0;
|
|
}
|
|
|
|
def BT : AMulxyI<0b0001011, (outs GPR:$dst), (ins GPR:$a, GPR:$b),
|
|
IIC_iMUL32, !strconcat(opc, "bt"), "\t$dst, $a, $b",
|
|
[(set GPR:$dst, (opnode (sext_inreg GPR:$a, i16),
|
|
(sra GPR:$b, (i32 16))))]>,
|
|
Requires<[IsARM, HasV5TE]> {
|
|
let Inst{5} = 0;
|
|
let Inst{6} = 1;
|
|
}
|
|
|
|
def TB : AMulxyI<0b0001011, (outs GPR:$dst), (ins GPR:$a, GPR:$b),
|
|
IIC_iMUL32, !strconcat(opc, "tb"), "\t$dst, $a, $b",
|
|
[(set GPR:$dst, (opnode (sra GPR:$a, (i32 16)),
|
|
(sext_inreg GPR:$b, i16)))]>,
|
|
Requires<[IsARM, HasV5TE]> {
|
|
let Inst{5} = 1;
|
|
let Inst{6} = 0;
|
|
}
|
|
|
|
def TT : AMulxyI<0b0001011, (outs GPR:$dst), (ins GPR:$a, GPR:$b),
|
|
IIC_iMUL32, !strconcat(opc, "tt"), "\t$dst, $a, $b",
|
|
[(set GPR:$dst, (opnode (sra GPR:$a, (i32 16)),
|
|
(sra GPR:$b, (i32 16))))]>,
|
|
Requires<[IsARM, HasV5TE]> {
|
|
let Inst{5} = 1;
|
|
let Inst{6} = 1;
|
|
}
|
|
|
|
def WB : AMulxyI<0b0001001, (outs GPR:$dst), (ins GPR:$a, GPR:$b),
|
|
IIC_iMUL16, !strconcat(opc, "wb"), "\t$dst, $a, $b",
|
|
[(set GPR:$dst, (sra (opnode GPR:$a,
|
|
(sext_inreg GPR:$b, i16)), (i32 16)))]>,
|
|
Requires<[IsARM, HasV5TE]> {
|
|
let Inst{5} = 1;
|
|
let Inst{6} = 0;
|
|
}
|
|
|
|
def WT : AMulxyI<0b0001001, (outs GPR:$dst), (ins GPR:$a, GPR:$b),
|
|
IIC_iMUL16, !strconcat(opc, "wt"), "\t$dst, $a, $b",
|
|
[(set GPR:$dst, (sra (opnode GPR:$a,
|
|
(sra GPR:$b, (i32 16))), (i32 16)))]>,
|
|
Requires<[IsARM, HasV5TE]> {
|
|
let Inst{5} = 1;
|
|
let Inst{6} = 1;
|
|
}
|
|
}
|
|
|
|
|
|
multiclass AI_smla<string opc, PatFrag opnode> {
|
|
def BB : AMulxyI<0b0001000, (outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc),
|
|
IIC_iMAC16, !strconcat(opc, "bb"), "\t$dst, $a, $b, $acc",
|
|
[(set GPR:$dst, (add GPR:$acc,
|
|
(opnode (sext_inreg GPR:$a, i16),
|
|
(sext_inreg GPR:$b, i16))))]>,
|
|
Requires<[IsARM, HasV5TE]> {
|
|
let Inst{5} = 0;
|
|
let Inst{6} = 0;
|
|
}
|
|
|
|
def BT : AMulxyI<0b0001000, (outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc),
|
|
IIC_iMAC16, !strconcat(opc, "bt"), "\t$dst, $a, $b, $acc",
|
|
[(set GPR:$dst, (add GPR:$acc, (opnode (sext_inreg GPR:$a, i16),
|
|
(sra GPR:$b, (i32 16)))))]>,
|
|
Requires<[IsARM, HasV5TE]> {
|
|
let Inst{5} = 0;
|
|
let Inst{6} = 1;
|
|
}
|
|
|
|
def TB : AMulxyI<0b0001000, (outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc),
|
|
IIC_iMAC16, !strconcat(opc, "tb"), "\t$dst, $a, $b, $acc",
|
|
[(set GPR:$dst, (add GPR:$acc, (opnode (sra GPR:$a, (i32 16)),
|
|
(sext_inreg GPR:$b, i16))))]>,
|
|
Requires<[IsARM, HasV5TE]> {
|
|
let Inst{5} = 1;
|
|
let Inst{6} = 0;
|
|
}
|
|
|
|
def TT : AMulxyI<0b0001000, (outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc),
|
|
IIC_iMAC16, !strconcat(opc, "tt"), "\t$dst, $a, $b, $acc",
|
|
[(set GPR:$dst, (add GPR:$acc, (opnode (sra GPR:$a, (i32 16)),
|
|
(sra GPR:$b, (i32 16)))))]>,
|
|
Requires<[IsARM, HasV5TE]> {
|
|
let Inst{5} = 1;
|
|
let Inst{6} = 1;
|
|
}
|
|
|
|
def WB : AMulxyI<0b0001001, (outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc),
|
|
IIC_iMAC16, !strconcat(opc, "wb"), "\t$dst, $a, $b, $acc",
|
|
[(set GPR:$dst, (add GPR:$acc, (sra (opnode GPR:$a,
|
|
(sext_inreg GPR:$b, i16)), (i32 16))))]>,
|
|
Requires<[IsARM, HasV5TE]> {
|
|
let Inst{5} = 0;
|
|
let Inst{6} = 0;
|
|
}
|
|
|
|
def WT : AMulxyI<0b0001001, (outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc),
|
|
IIC_iMAC16, !strconcat(opc, "wt"), "\t$dst, $a, $b, $acc",
|
|
[(set GPR:$dst, (add GPR:$acc, (sra (opnode GPR:$a,
|
|
(sra GPR:$b, (i32 16))), (i32 16))))]>,
|
|
Requires<[IsARM, HasV5TE]> {
|
|
let Inst{5} = 0;
|
|
let Inst{6} = 1;
|
|
}
|
|
}
|
|
|
|
defm SMUL : AI_smul<"smul", BinOpFrag<(mul node:$LHS, node:$RHS)>>;
|
|
defm SMLA : AI_smla<"smla", BinOpFrag<(mul node:$LHS, node:$RHS)>>;
|
|
|
|
// Halfword multiply accumulate long: SMLAL<x><y> -- for disassembly only
|
|
def SMLALBB : AMulxyI<0b0001010,(outs GPR:$ldst,GPR:$hdst),(ins GPR:$a,GPR:$b),
|
|
IIC_iMAC64, "smlalbb", "\t$ldst, $hdst, $a, $b",
|
|
[/* For disassembly only; pattern left blank */]>,
|
|
Requires<[IsARM, HasV5TE]> {
|
|
let Inst{5} = 0;
|
|
let Inst{6} = 0;
|
|
}
|
|
|
|
def SMLALBT : AMulxyI<0b0001010,(outs GPR:$ldst,GPR:$hdst),(ins GPR:$a,GPR:$b),
|
|
IIC_iMAC64, "smlalbt", "\t$ldst, $hdst, $a, $b",
|
|
[/* For disassembly only; pattern left blank */]>,
|
|
Requires<[IsARM, HasV5TE]> {
|
|
let Inst{5} = 0;
|
|
let Inst{6} = 1;
|
|
}
|
|
|
|
def SMLALTB : AMulxyI<0b0001010,(outs GPR:$ldst,GPR:$hdst),(ins GPR:$a,GPR:$b),
|
|
IIC_iMAC64, "smlaltb", "\t$ldst, $hdst, $a, $b",
|
|
[/* For disassembly only; pattern left blank */]>,
|
|
Requires<[IsARM, HasV5TE]> {
|
|
let Inst{5} = 1;
|
|
let Inst{6} = 0;
|
|
}
|
|
|
|
def SMLALTT : AMulxyI<0b0001010,(outs GPR:$ldst,GPR:$hdst),(ins GPR:$a,GPR:$b),
|
|
IIC_iMAC64, "smlaltt", "\t$ldst, $hdst, $a, $b",
|
|
[/* For disassembly only; pattern left blank */]>,
|
|
Requires<[IsARM, HasV5TE]> {
|
|
let Inst{5} = 1;
|
|
let Inst{6} = 1;
|
|
}
|
|
|
|
// Helper class for AI_smld -- for disassembly only
|
|
class AMulDualI<bit long, bit sub, bit swap, dag oops, dag iops,
|
|
InstrItinClass itin, string opc, string asm>
|
|
: AI<oops, iops, MulFrm, itin, opc, asm, []>, Requires<[IsARM, HasV6]> {
|
|
let Inst{4} = 1;
|
|
let Inst{5} = swap;
|
|
let Inst{6} = sub;
|
|
let Inst{7} = 0;
|
|
let Inst{21-20} = 0b00;
|
|
let Inst{22} = long;
|
|
let Inst{27-23} = 0b01110;
|
|
}
|
|
|
|
multiclass AI_smld<bit sub, string opc> {
|
|
|
|
def D : AMulDualI<0, sub, 0, (outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc),
|
|
NoItinerary, !strconcat(opc, "d"), "\t$dst, $a, $b, $acc">;
|
|
|
|
def DX : AMulDualI<0, sub, 1, (outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc),
|
|
NoItinerary, !strconcat(opc, "dx"), "\t$dst, $a, $b, $acc">;
|
|
|
|
def LD : AMulDualI<1, sub, 0, (outs GPR:$ldst,GPR:$hdst), (ins GPR:$a,GPR:$b),
|
|
NoItinerary, !strconcat(opc, "ld"), "\t$ldst, $hdst, $a, $b">;
|
|
|
|
def LDX : AMulDualI<1, sub, 1, (outs GPR:$ldst,GPR:$hdst),(ins GPR:$a,GPR:$b),
|
|
NoItinerary, !strconcat(opc, "ldx"),"\t$ldst, $hdst, $a, $b">;
|
|
|
|
}
|
|
|
|
defm SMLA : AI_smld<0, "smla">;
|
|
defm SMLS : AI_smld<1, "smls">;
|
|
|
|
multiclass AI_sdml<bit sub, string opc> {
|
|
|
|
def D : AMulDualI<0, sub, 0, (outs GPR:$dst), (ins GPR:$a, GPR:$b),
|
|
NoItinerary, !strconcat(opc, "d"), "\t$dst, $a, $b"> {
|
|
let Inst{15-12} = 0b1111;
|
|
}
|
|
|
|
def DX : AMulDualI<0, sub, 1, (outs GPR:$dst), (ins GPR:$a, GPR:$b),
|
|
NoItinerary, !strconcat(opc, "dx"), "\t$dst, $a, $b"> {
|
|
let Inst{15-12} = 0b1111;
|
|
}
|
|
|
|
}
|
|
|
|
defm SMUA : AI_sdml<0, "smua">;
|
|
defm SMUS : AI_sdml<1, "smus">;
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// Misc. Arithmetic Instructions.
|
|
//
|
|
|
|
def CLZ : AMiscA1I<0b000010110, (outs GPR:$dst), (ins GPR:$src), IIC_iUNAr,
|
|
"clz", "\t$dst, $src",
|
|
[(set GPR:$dst, (ctlz GPR:$src))]>, Requires<[IsARM, HasV5T]> {
|
|
let Inst{7-4} = 0b0001;
|
|
let Inst{11-8} = 0b1111;
|
|
let Inst{19-16} = 0b1111;
|
|
}
|
|
|
|
def RBIT : AMiscA1I<0b01101111, (outs GPR:$dst), (ins GPR:$src), IIC_iUNAr,
|
|
"rbit", "\t$dst, $src",
|
|
[(set GPR:$dst, (ARMrbit GPR:$src))]>,
|
|
Requires<[IsARM, HasV6T2]> {
|
|
let Inst{7-4} = 0b0011;
|
|
let Inst{11-8} = 0b1111;
|
|
let Inst{19-16} = 0b1111;
|
|
}
|
|
|
|
def REV : AMiscA1I<0b01101011, (outs GPR:$dst), (ins GPR:$src), IIC_iUNAr,
|
|
"rev", "\t$dst, $src",
|
|
[(set GPR:$dst, (bswap GPR:$src))]>, Requires<[IsARM, HasV6]> {
|
|
let Inst{7-4} = 0b0011;
|
|
let Inst{11-8} = 0b1111;
|
|
let Inst{19-16} = 0b1111;
|
|
}
|
|
|
|
def REV16 : AMiscA1I<0b01101011, (outs GPR:$dst), (ins GPR:$src), IIC_iUNAr,
|
|
"rev16", "\t$dst, $src",
|
|
[(set GPR:$dst,
|
|
(or (and (srl GPR:$src, (i32 8)), 0xFF),
|
|
(or (and (shl GPR:$src, (i32 8)), 0xFF00),
|
|
(or (and (srl GPR:$src, (i32 8)), 0xFF0000),
|
|
(and (shl GPR:$src, (i32 8)), 0xFF000000)))))]>,
|
|
Requires<[IsARM, HasV6]> {
|
|
let Inst{7-4} = 0b1011;
|
|
let Inst{11-8} = 0b1111;
|
|
let Inst{19-16} = 0b1111;
|
|
}
|
|
|
|
def REVSH : AMiscA1I<0b01101111, (outs GPR:$dst), (ins GPR:$src), IIC_iUNAr,
|
|
"revsh", "\t$dst, $src",
|
|
[(set GPR:$dst,
|
|
(sext_inreg
|
|
(or (srl (and GPR:$src, 0xFF00), (i32 8)),
|
|
(shl GPR:$src, (i32 8))), i16))]>,
|
|
Requires<[IsARM, HasV6]> {
|
|
let Inst{7-4} = 0b1011;
|
|
let Inst{11-8} = 0b1111;
|
|
let Inst{19-16} = 0b1111;
|
|
}
|
|
|
|
def PKHBT : AMiscA1I<0b01101000, (outs GPR:$dst),
|
|
(ins GPR:$src1, GPR:$src2, i32imm:$shamt),
|
|
IIC_iALUsi, "pkhbt", "\t$dst, $src1, $src2, lsl $shamt",
|
|
[(set GPR:$dst, (or (and GPR:$src1, 0xFFFF),
|
|
(and (shl GPR:$src2, (i32 imm:$shamt)),
|
|
0xFFFF0000)))]>,
|
|
Requires<[IsARM, HasV6]> {
|
|
let Inst{6-4} = 0b001;
|
|
}
|
|
|
|
// Alternate cases for PKHBT where identities eliminate some nodes.
|
|
def : ARMV6Pat<(or (and GPR:$src1, 0xFFFF), (and GPR:$src2, 0xFFFF0000)),
|
|
(PKHBT GPR:$src1, GPR:$src2, 0)>;
|
|
def : ARMV6Pat<(or (and GPR:$src1, 0xFFFF), (shl GPR:$src2, imm16_31:$shamt)),
|
|
(PKHBT GPR:$src1, GPR:$src2, imm16_31:$shamt)>;
|
|
|
|
|
|
def PKHTB : AMiscA1I<0b01101000, (outs GPR:$dst),
|
|
(ins GPR:$src1, GPR:$src2, i32imm:$shamt),
|
|
IIC_iALUsi, "pkhtb", "\t$dst, $src1, $src2, asr $shamt",
|
|
[(set GPR:$dst, (or (and GPR:$src1, 0xFFFF0000),
|
|
(and (sra GPR:$src2, imm16_31:$shamt),
|
|
0xFFFF)))]>, Requires<[IsARM, HasV6]> {
|
|
let Inst{6-4} = 0b101;
|
|
}
|
|
|
|
// Alternate cases for PKHTB where identities eliminate some nodes. Note that
|
|
// a shift amount of 0 is *not legal* here, it is PKHBT instead.
|
|
def : ARMV6Pat<(or (and GPR:$src1, 0xFFFF0000), (srl GPR:$src2, (i32 16))),
|
|
(PKHTB GPR:$src1, GPR:$src2, 16)>;
|
|
def : ARMV6Pat<(or (and GPR:$src1, 0xFFFF0000),
|
|
(and (srl GPR:$src2, imm1_15:$shamt), 0xFFFF)),
|
|
(PKHTB GPR:$src1, GPR:$src2, imm1_15:$shamt)>;
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// Comparison Instructions...
|
|
//
|
|
|
|
defm CMP : AI1_cmp_irs<0b1010, "cmp",
|
|
BinOpFrag<(ARMcmp node:$LHS, node:$RHS)>>;
|
|
//FIXME: Disable CMN, as CCodes are backwards from compare expectations
|
|
// Compare-to-zero still works out, just not the relationals
|
|
//defm CMN : AI1_cmp_irs<0b1011, "cmn",
|
|
// BinOpFrag<(ARMcmp node:$LHS,(ineg node:$RHS))>>;
|
|
|
|
// Note that TST/TEQ don't set all the same flags that CMP does!
|
|
defm TST : AI1_cmp_irs<0b1000, "tst",
|
|
BinOpFrag<(ARMcmpZ (and node:$LHS, node:$RHS), 0)>, 1>;
|
|
defm TEQ : AI1_cmp_irs<0b1001, "teq",
|
|
BinOpFrag<(ARMcmpZ (xor node:$LHS, node:$RHS), 0)>, 1>;
|
|
|
|
defm CMPz : AI1_cmp_irs<0b1010, "cmp",
|
|
BinOpFrag<(ARMcmpZ node:$LHS, node:$RHS)>>;
|
|
defm CMNz : AI1_cmp_irs<0b1011, "cmn",
|
|
BinOpFrag<(ARMcmpZ node:$LHS,(ineg node:$RHS))>>;
|
|
|
|
//def : ARMPat<(ARMcmp GPR:$src, so_imm_neg:$imm),
|
|
// (CMNri GPR:$src, so_imm_neg:$imm)>;
|
|
|
|
def : ARMPat<(ARMcmpZ GPR:$src, so_imm_neg:$imm),
|
|
(CMNzri GPR:$src, so_imm_neg:$imm)>;
|
|
|
|
|
|
// Conditional moves
|
|
// FIXME: should be able to write a pattern for ARMcmov, but can't use
|
|
// a two-value operand where a dag node expects two operands. :(
|
|
def MOVCCr : AI1<0b1101, (outs GPR:$dst), (ins GPR:$false, GPR:$true), DPFrm,
|
|
IIC_iCMOVr, "mov", "\t$dst, $true",
|
|
[/*(set GPR:$dst, (ARMcmov GPR:$false, GPR:$true, imm:$cc, CCR:$ccr))*/]>,
|
|
RegConstraint<"$false = $dst">, UnaryDP {
|
|
let Inst{11-4} = 0b00000000;
|
|
let Inst{25} = 0;
|
|
}
|
|
|
|
def MOVCCs : AI1<0b1101, (outs GPR:$dst),
|
|
(ins GPR:$false, so_reg:$true), DPSoRegFrm, IIC_iCMOVsr,
|
|
"mov", "\t$dst, $true",
|
|
[/*(set GPR:$dst, (ARMcmov GPR:$false, so_reg:$true, imm:$cc, CCR:$ccr))*/]>,
|
|
RegConstraint<"$false = $dst">, UnaryDP {
|
|
let Inst{25} = 0;
|
|
}
|
|
|
|
def MOVCCi : AI1<0b1101, (outs GPR:$dst),
|
|
(ins GPR:$false, so_imm:$true), DPFrm, IIC_iCMOVi,
|
|
"mov", "\t$dst, $true",
|
|
[/*(set GPR:$dst, (ARMcmov GPR:$false, so_imm:$true, imm:$cc, CCR:$ccr))*/]>,
|
|
RegConstraint<"$false = $dst">, UnaryDP {
|
|
let Inst{25} = 1;
|
|
}
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// Atomic operations intrinsics
|
|
//
|
|
|
|
// memory barriers protect the atomic sequences
|
|
let hasSideEffects = 1 in {
|
|
def Int_MemBarrierV7 : AInoP<(outs), (ins),
|
|
Pseudo, NoItinerary,
|
|
"dmb", "",
|
|
[(ARMMemBarrierV7)]>,
|
|
Requires<[IsARM, HasV7]> {
|
|
let Inst{31-4} = 0xf57ff05;
|
|
// FIXME: add support for options other than a full system DMB
|
|
// See DMB disassembly-only variants below.
|
|
let Inst{3-0} = 0b1111;
|
|
}
|
|
|
|
def Int_SyncBarrierV7 : AInoP<(outs), (ins),
|
|
Pseudo, NoItinerary,
|
|
"dsb", "",
|
|
[(ARMSyncBarrierV7)]>,
|
|
Requires<[IsARM, HasV7]> {
|
|
let Inst{31-4} = 0xf57ff04;
|
|
// FIXME: add support for options other than a full system DSB
|
|
// See DSB disassembly-only variants below.
|
|
let Inst{3-0} = 0b1111;
|
|
}
|
|
|
|
def Int_MemBarrierV6 : AInoP<(outs), (ins GPR:$zero),
|
|
Pseudo, NoItinerary,
|
|
"mcr", "\tp15, 0, $zero, c7, c10, 5",
|
|
[(ARMMemBarrierV6 GPR:$zero)]>,
|
|
Requires<[IsARM, HasV6]> {
|
|
// FIXME: add support for options other than a full system DMB
|
|
// FIXME: add encoding
|
|
}
|
|
|
|
def Int_SyncBarrierV6 : AInoP<(outs), (ins GPR:$zero),
|
|
Pseudo, NoItinerary,
|
|
"mcr", "\tp15, 0, $zero, c7, c10, 4",
|
|
[(ARMSyncBarrierV6 GPR:$zero)]>,
|
|
Requires<[IsARM, HasV6]> {
|
|
// FIXME: add support for options other than a full system DSB
|
|
// FIXME: add encoding
|
|
}
|
|
}
|
|
|
|
// Helper class for multiclass MemB -- for disassembly only
|
|
class AMBI<string opc, string asm>
|
|
: AInoP<(outs), (ins), MiscFrm, NoItinerary, opc, asm,
|
|
[/* For disassembly only; pattern left blank */]>,
|
|
Requires<[IsARM, HasV7]> {
|
|
let Inst{31-20} = 0xf57;
|
|
}
|
|
|
|
multiclass MemB<bits<4> op7_4, string opc> {
|
|
|
|
def st : AMBI<opc, "\tst"> {
|
|
let Inst{7-4} = op7_4;
|
|
let Inst{3-0} = 0b1110;
|
|
}
|
|
|
|
def ish : AMBI<opc, "\tish"> {
|
|
let Inst{7-4} = op7_4;
|
|
let Inst{3-0} = 0b1011;
|
|
}
|
|
|
|
def ishst : AMBI<opc, "\tishst"> {
|
|
let Inst{7-4} = op7_4;
|
|
let Inst{3-0} = 0b1010;
|
|
}
|
|
|
|
def nsh : AMBI<opc, "\tnsh"> {
|
|
let Inst{7-4} = op7_4;
|
|
let Inst{3-0} = 0b0111;
|
|
}
|
|
|
|
def nshst : AMBI<opc, "\tnshst"> {
|
|
let Inst{7-4} = op7_4;
|
|
let Inst{3-0} = 0b0110;
|
|
}
|
|
|
|
def osh : AMBI<opc, "\tosh"> {
|
|
let Inst{7-4} = op7_4;
|
|
let Inst{3-0} = 0b0011;
|
|
}
|
|
|
|
def oshst : AMBI<opc, "\toshst"> {
|
|
let Inst{7-4} = op7_4;
|
|
let Inst{3-0} = 0b0010;
|
|
}
|
|
}
|
|
|
|
// These DMB variants are for disassembly only.
|
|
defm DMB : MemB<0b0101, "dmb">;
|
|
|
|
// These DSB variants are for disassembly only.
|
|
defm DSB : MemB<0b0100, "dsb">;
|
|
|
|
// ISB has only full system option -- for disassembly only
|
|
def ISBsy : AMBI<"isb", ""> {
|
|
let Inst{7-4} = 0b0110;
|
|
let Inst{3-0} = 0b1111;
|
|
}
|
|
|
|
let usesCustomInserter = 1 in {
|
|
let Uses = [CPSR] in {
|
|
def ATOMIC_LOAD_ADD_I8 : PseudoInst<
|
|
(outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
|
|
"${:comment} ATOMIC_LOAD_ADD_I8 PSEUDO!",
|
|
[(set GPR:$dst, (atomic_load_add_8 GPR:$ptr, GPR:$incr))]>;
|
|
def ATOMIC_LOAD_SUB_I8 : PseudoInst<
|
|
(outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
|
|
"${:comment} ATOMIC_LOAD_SUB_I8 PSEUDO!",
|
|
[(set GPR:$dst, (atomic_load_sub_8 GPR:$ptr, GPR:$incr))]>;
|
|
def ATOMIC_LOAD_AND_I8 : PseudoInst<
|
|
(outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
|
|
"${:comment} ATOMIC_LOAD_AND_I8 PSEUDO!",
|
|
[(set GPR:$dst, (atomic_load_and_8 GPR:$ptr, GPR:$incr))]>;
|
|
def ATOMIC_LOAD_OR_I8 : PseudoInst<
|
|
(outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
|
|
"${:comment} ATOMIC_LOAD_OR_I8 PSEUDO!",
|
|
[(set GPR:$dst, (atomic_load_or_8 GPR:$ptr, GPR:$incr))]>;
|
|
def ATOMIC_LOAD_XOR_I8 : PseudoInst<
|
|
(outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
|
|
"${:comment} ATOMIC_LOAD_XOR_I8 PSEUDO!",
|
|
[(set GPR:$dst, (atomic_load_xor_8 GPR:$ptr, GPR:$incr))]>;
|
|
def ATOMIC_LOAD_NAND_I8 : PseudoInst<
|
|
(outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
|
|
"${:comment} ATOMIC_LOAD_NAND_I8 PSEUDO!",
|
|
[(set GPR:$dst, (atomic_load_nand_8 GPR:$ptr, GPR:$incr))]>;
|
|
def ATOMIC_LOAD_ADD_I16 : PseudoInst<
|
|
(outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
|
|
"${:comment} ATOMIC_LOAD_ADD_I16 PSEUDO!",
|
|
[(set GPR:$dst, (atomic_load_add_16 GPR:$ptr, GPR:$incr))]>;
|
|
def ATOMIC_LOAD_SUB_I16 : PseudoInst<
|
|
(outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
|
|
"${:comment} ATOMIC_LOAD_SUB_I16 PSEUDO!",
|
|
[(set GPR:$dst, (atomic_load_sub_16 GPR:$ptr, GPR:$incr))]>;
|
|
def ATOMIC_LOAD_AND_I16 : PseudoInst<
|
|
(outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
|
|
"${:comment} ATOMIC_LOAD_AND_I16 PSEUDO!",
|
|
[(set GPR:$dst, (atomic_load_and_16 GPR:$ptr, GPR:$incr))]>;
|
|
def ATOMIC_LOAD_OR_I16 : PseudoInst<
|
|
(outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
|
|
"${:comment} ATOMIC_LOAD_OR_I16 PSEUDO!",
|
|
[(set GPR:$dst, (atomic_load_or_16 GPR:$ptr, GPR:$incr))]>;
|
|
def ATOMIC_LOAD_XOR_I16 : PseudoInst<
|
|
(outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
|
|
"${:comment} ATOMIC_LOAD_XOR_I16 PSEUDO!",
|
|
[(set GPR:$dst, (atomic_load_xor_16 GPR:$ptr, GPR:$incr))]>;
|
|
def ATOMIC_LOAD_NAND_I16 : PseudoInst<
|
|
(outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
|
|
"${:comment} ATOMIC_LOAD_NAND_I16 PSEUDO!",
|
|
[(set GPR:$dst, (atomic_load_nand_16 GPR:$ptr, GPR:$incr))]>;
|
|
def ATOMIC_LOAD_ADD_I32 : PseudoInst<
|
|
(outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
|
|
"${:comment} ATOMIC_LOAD_ADD_I32 PSEUDO!",
|
|
[(set GPR:$dst, (atomic_load_add_32 GPR:$ptr, GPR:$incr))]>;
|
|
def ATOMIC_LOAD_SUB_I32 : PseudoInst<
|
|
(outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
|
|
"${:comment} ATOMIC_LOAD_SUB_I32 PSEUDO!",
|
|
[(set GPR:$dst, (atomic_load_sub_32 GPR:$ptr, GPR:$incr))]>;
|
|
def ATOMIC_LOAD_AND_I32 : PseudoInst<
|
|
(outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
|
|
"${:comment} ATOMIC_LOAD_AND_I32 PSEUDO!",
|
|
[(set GPR:$dst, (atomic_load_and_32 GPR:$ptr, GPR:$incr))]>;
|
|
def ATOMIC_LOAD_OR_I32 : PseudoInst<
|
|
(outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
|
|
"${:comment} ATOMIC_LOAD_OR_I32 PSEUDO!",
|
|
[(set GPR:$dst, (atomic_load_or_32 GPR:$ptr, GPR:$incr))]>;
|
|
def ATOMIC_LOAD_XOR_I32 : PseudoInst<
|
|
(outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
|
|
"${:comment} ATOMIC_LOAD_XOR_I32 PSEUDO!",
|
|
[(set GPR:$dst, (atomic_load_xor_32 GPR:$ptr, GPR:$incr))]>;
|
|
def ATOMIC_LOAD_NAND_I32 : PseudoInst<
|
|
(outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
|
|
"${:comment} ATOMIC_LOAD_NAND_I32 PSEUDO!",
|
|
[(set GPR:$dst, (atomic_load_nand_32 GPR:$ptr, GPR:$incr))]>;
|
|
|
|
def ATOMIC_SWAP_I8 : PseudoInst<
|
|
(outs GPR:$dst), (ins GPR:$ptr, GPR:$new), NoItinerary,
|
|
"${:comment} ATOMIC_SWAP_I8 PSEUDO!",
|
|
[(set GPR:$dst, (atomic_swap_8 GPR:$ptr, GPR:$new))]>;
|
|
def ATOMIC_SWAP_I16 : PseudoInst<
|
|
(outs GPR:$dst), (ins GPR:$ptr, GPR:$new), NoItinerary,
|
|
"${:comment} ATOMIC_SWAP_I16 PSEUDO!",
|
|
[(set GPR:$dst, (atomic_swap_16 GPR:$ptr, GPR:$new))]>;
|
|
def ATOMIC_SWAP_I32 : PseudoInst<
|
|
(outs GPR:$dst), (ins GPR:$ptr, GPR:$new), NoItinerary,
|
|
"${:comment} ATOMIC_SWAP_I32 PSEUDO!",
|
|
[(set GPR:$dst, (atomic_swap_32 GPR:$ptr, GPR:$new))]>;
|
|
|
|
def ATOMIC_CMP_SWAP_I8 : PseudoInst<
|
|
(outs GPR:$dst), (ins GPR:$ptr, GPR:$old, GPR:$new), NoItinerary,
|
|
"${:comment} ATOMIC_CMP_SWAP_I8 PSEUDO!",
|
|
[(set GPR:$dst, (atomic_cmp_swap_8 GPR:$ptr, GPR:$old, GPR:$new))]>;
|
|
def ATOMIC_CMP_SWAP_I16 : PseudoInst<
|
|
(outs GPR:$dst), (ins GPR:$ptr, GPR:$old, GPR:$new), NoItinerary,
|
|
"${:comment} ATOMIC_CMP_SWAP_I16 PSEUDO!",
|
|
[(set GPR:$dst, (atomic_cmp_swap_16 GPR:$ptr, GPR:$old, GPR:$new))]>;
|
|
def ATOMIC_CMP_SWAP_I32 : PseudoInst<
|
|
(outs GPR:$dst), (ins GPR:$ptr, GPR:$old, GPR:$new), NoItinerary,
|
|
"${:comment} ATOMIC_CMP_SWAP_I32 PSEUDO!",
|
|
[(set GPR:$dst, (atomic_cmp_swap_32 GPR:$ptr, GPR:$old, GPR:$new))]>;
|
|
}
|
|
}
|
|
|
|
let mayLoad = 1 in {
|
|
def LDREXB : AIldrex<0b10, (outs GPR:$dest), (ins GPR:$ptr), NoItinerary,
|
|
"ldrexb", "\t$dest, [$ptr]",
|
|
[]>;
|
|
def LDREXH : AIldrex<0b11, (outs GPR:$dest), (ins GPR:$ptr), NoItinerary,
|
|
"ldrexh", "\t$dest, [$ptr]",
|
|
[]>;
|
|
def LDREX : AIldrex<0b00, (outs GPR:$dest), (ins GPR:$ptr), NoItinerary,
|
|
"ldrex", "\t$dest, [$ptr]",
|
|
[]>;
|
|
def LDREXD : AIldrex<0b01, (outs GPR:$dest, GPR:$dest2), (ins GPR:$ptr),
|
|
NoItinerary,
|
|
"ldrexd", "\t$dest, $dest2, [$ptr]",
|
|
[]>;
|
|
}
|
|
|
|
let mayStore = 1, Constraints = "@earlyclobber $success" in {
|
|
def STREXB : AIstrex<0b10, (outs GPR:$success), (ins GPR:$src, GPR:$ptr),
|
|
NoItinerary,
|
|
"strexb", "\t$success, $src, [$ptr]",
|
|
[]>;
|
|
def STREXH : AIstrex<0b11, (outs GPR:$success), (ins GPR:$src, GPR:$ptr),
|
|
NoItinerary,
|
|
"strexh", "\t$success, $src, [$ptr]",
|
|
[]>;
|
|
def STREX : AIstrex<0b00, (outs GPR:$success), (ins GPR:$src, GPR:$ptr),
|
|
NoItinerary,
|
|
"strex", "\t$success, $src, [$ptr]",
|
|
[]>;
|
|
def STREXD : AIstrex<0b01, (outs GPR:$success),
|
|
(ins GPR:$src, GPR:$src2, GPR:$ptr),
|
|
NoItinerary,
|
|
"strexd", "\t$success, $src, $src2, [$ptr]",
|
|
[]>;
|
|
}
|
|
|
|
// Clear-Exclusive is for disassembly only.
|
|
def CLREX : AXI<(outs), (ins), MiscFrm, NoItinerary, "clrex",
|
|
[/* For disassembly only; pattern left blank */]>,
|
|
Requires<[IsARM, HasV7]> {
|
|
let Inst{31-20} = 0xf57;
|
|
let Inst{7-4} = 0b0001;
|
|
}
|
|
|
|
// SWP/SWPB are deprecated in V6/V7 and for disassembly only.
|
|
let mayLoad = 1 in {
|
|
def SWP : AI<(outs GPR:$dst), (ins GPR:$src, GPR:$ptr), LdStExFrm, NoItinerary,
|
|
"swp", "\t$dst, $src, [$ptr]",
|
|
[/* For disassembly only; pattern left blank */]> {
|
|
let Inst{27-23} = 0b00010;
|
|
let Inst{22} = 0; // B = 0
|
|
let Inst{21-20} = 0b00;
|
|
let Inst{7-4} = 0b1001;
|
|
}
|
|
|
|
def SWPB : AI<(outs GPR:$dst), (ins GPR:$src, GPR:$ptr), LdStExFrm, NoItinerary,
|
|
"swpb", "\t$dst, $src, [$ptr]",
|
|
[/* For disassembly only; pattern left blank */]> {
|
|
let Inst{27-23} = 0b00010;
|
|
let Inst{22} = 1; // B = 1
|
|
let Inst{21-20} = 0b00;
|
|
let Inst{7-4} = 0b1001;
|
|
}
|
|
}
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// TLS Instructions
|
|
//
|
|
|
|
// __aeabi_read_tp preserves the registers r1-r3.
|
|
let isCall = 1,
|
|
Defs = [R0, R12, LR, CPSR] in {
|
|
def TPsoft : ABXI<0b1011, (outs), (ins), IIC_Br,
|
|
"bl\t__aeabi_read_tp",
|
|
[(set R0, ARMthread_pointer)]>;
|
|
}
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// SJLJ Exception handling intrinsics
|
|
// eh_sjlj_setjmp() is an instruction sequence to store the return
|
|
// address and save #0 in R0 for the non-longjmp case.
|
|
// Since by its nature we may be coming from some other function to get
|
|
// here, and we're using the stack frame for the containing function to
|
|
// save/restore registers, we can't keep anything live in regs across
|
|
// the eh_sjlj_setjmp(), else it will almost certainly have been tromped upon
|
|
// when we get here from a longjmp(). We force everthing out of registers
|
|
// except for our own input by listing the relevant registers in Defs. By
|
|
// doing so, we also cause the prologue/epilogue code to actively preserve
|
|
// all of the callee-saved resgisters, which is exactly what we want.
|
|
// A constant value is passed in $val, and we use the location as a scratch.
|
|
let Defs =
|
|
[ R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, LR, D0,
|
|
D1, D2, D3, D4, D5, D6, D7, D8, D9, D10, D11, D12, D13, D14, D15,
|
|
D16, D17, D18, D19, D20, D21, D22, D23, D24, D25, D26, D27, D28, D29, D30,
|
|
D31 ] in {
|
|
def Int_eh_sjlj_setjmp : XI<(outs), (ins GPR:$src, GPR:$val),
|
|
AddrModeNone, SizeSpecial, IndexModeNone,
|
|
Pseudo, NoItinerary,
|
|
"str\tsp, [$src, #+8] @ eh_setjmp begin\n\t"
|
|
"add\t$val, pc, #8\n\t"
|
|
"str\t$val, [$src, #+4]\n\t"
|
|
"mov\tr0, #0\n\t"
|
|
"add\tpc, pc, #0\n\t"
|
|
"mov\tr0, #1 @ eh_setjmp end", "",
|
|
[(set R0, (ARMeh_sjlj_setjmp GPR:$src, GPR:$val))]>;
|
|
}
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// Non-Instruction Patterns
|
|
//
|
|
|
|
// Large immediate handling.
|
|
|
|
// Two piece so_imms.
|
|
let isReMaterializable = 1 in
|
|
def MOVi2pieces : AI1x2<(outs GPR:$dst), (ins so_imm2part:$src),
|
|
Pseudo, IIC_iMOVi,
|
|
"mov", "\t$dst, $src",
|
|
[(set GPR:$dst, so_imm2part:$src)]>,
|
|
Requires<[IsARM, NoV6T2]>;
|
|
|
|
def : ARMPat<(or GPR:$LHS, so_imm2part:$RHS),
|
|
(ORRri (ORRri GPR:$LHS, (so_imm2part_1 imm:$RHS)),
|
|
(so_imm2part_2 imm:$RHS))>;
|
|
def : ARMPat<(xor GPR:$LHS, so_imm2part:$RHS),
|
|
(EORri (EORri GPR:$LHS, (so_imm2part_1 imm:$RHS)),
|
|
(so_imm2part_2 imm:$RHS))>;
|
|
def : ARMPat<(add GPR:$LHS, so_imm2part:$RHS),
|
|
(ADDri (ADDri GPR:$LHS, (so_imm2part_1 imm:$RHS)),
|
|
(so_imm2part_2 imm:$RHS))>;
|
|
def : ARMPat<(add GPR:$LHS, so_neg_imm2part:$RHS),
|
|
(SUBri (SUBri GPR:$LHS, (so_neg_imm2part_1 imm:$RHS)),
|
|
(so_neg_imm2part_2 imm:$RHS))>;
|
|
|
|
// 32-bit immediate using movw + movt.
|
|
// This is a single pseudo instruction, the benefit is that it can be remat'd
|
|
// as a single unit instead of having to handle reg inputs.
|
|
// FIXME: Remove this when we can do generalized remat.
|
|
let isReMaterializable = 1 in
|
|
def MOVi32imm : AI1x2<(outs GPR:$dst), (ins i32imm:$src), Pseudo, IIC_iMOVi,
|
|
"movw", "\t$dst, ${src:lo16}\n\tmovt${p}\t$dst, ${src:hi16}",
|
|
[(set GPR:$dst, (i32 imm:$src))]>,
|
|
Requires<[IsARM, HasV6T2]>;
|
|
|
|
// ConstantPool, GlobalAddress, and JumpTable
|
|
def : ARMPat<(ARMWrapper tglobaladdr :$dst), (LEApcrel tglobaladdr :$dst)>,
|
|
Requires<[IsARM, DontUseMovt]>;
|
|
def : ARMPat<(ARMWrapper tconstpool :$dst), (LEApcrel tconstpool :$dst)>;
|
|
def : ARMPat<(ARMWrapper tglobaladdr :$dst), (MOVi32imm tglobaladdr :$dst)>,
|
|
Requires<[IsARM, UseMovt]>;
|
|
def : ARMPat<(ARMWrapperJT tjumptable:$dst, imm:$id),
|
|
(LEApcrelJT tjumptable:$dst, imm:$id)>;
|
|
|
|
// TODO: add,sub,and, 3-instr forms?
|
|
|
|
|
|
// Direct calls
|
|
def : ARMPat<(ARMcall texternalsym:$func), (BL texternalsym:$func)>,
|
|
Requires<[IsARM, IsNotDarwin]>;
|
|
def : ARMPat<(ARMcall texternalsym:$func), (BLr9 texternalsym:$func)>,
|
|
Requires<[IsARM, IsDarwin]>;
|
|
|
|
// zextload i1 -> zextload i8
|
|
def : ARMPat<(zextloadi1 addrmode2:$addr), (LDRB addrmode2:$addr)>;
|
|
|
|
// extload -> zextload
|
|
def : ARMPat<(extloadi1 addrmode2:$addr), (LDRB addrmode2:$addr)>;
|
|
def : ARMPat<(extloadi8 addrmode2:$addr), (LDRB addrmode2:$addr)>;
|
|
def : ARMPat<(extloadi16 addrmode3:$addr), (LDRH addrmode3:$addr)>;
|
|
|
|
def : ARMPat<(extloadi8 addrmodepc:$addr), (PICLDRB addrmodepc:$addr)>;
|
|
def : ARMPat<(extloadi16 addrmodepc:$addr), (PICLDRH addrmodepc:$addr)>;
|
|
|
|
// smul* and smla*
|
|
def : ARMV5TEPat<(mul (sra (shl GPR:$a, (i32 16)), (i32 16)),
|
|
(sra (shl GPR:$b, (i32 16)), (i32 16))),
|
|
(SMULBB GPR:$a, GPR:$b)>;
|
|
def : ARMV5TEPat<(mul sext_16_node:$a, sext_16_node:$b),
|
|
(SMULBB GPR:$a, GPR:$b)>;
|
|
def : ARMV5TEPat<(mul (sra (shl GPR:$a, (i32 16)), (i32 16)),
|
|
(sra GPR:$b, (i32 16))),
|
|
(SMULBT GPR:$a, GPR:$b)>;
|
|
def : ARMV5TEPat<(mul sext_16_node:$a, (sra GPR:$b, (i32 16))),
|
|
(SMULBT GPR:$a, GPR:$b)>;
|
|
def : ARMV5TEPat<(mul (sra GPR:$a, (i32 16)),
|
|
(sra (shl GPR:$b, (i32 16)), (i32 16))),
|
|
(SMULTB GPR:$a, GPR:$b)>;
|
|
def : ARMV5TEPat<(mul (sra GPR:$a, (i32 16)), sext_16_node:$b),
|
|
(SMULTB GPR:$a, GPR:$b)>;
|
|
def : ARMV5TEPat<(sra (mul GPR:$a, (sra (shl GPR:$b, (i32 16)), (i32 16))),
|
|
(i32 16)),
|
|
(SMULWB GPR:$a, GPR:$b)>;
|
|
def : ARMV5TEPat<(sra (mul GPR:$a, sext_16_node:$b), (i32 16)),
|
|
(SMULWB GPR:$a, GPR:$b)>;
|
|
|
|
def : ARMV5TEPat<(add GPR:$acc,
|
|
(mul (sra (shl GPR:$a, (i32 16)), (i32 16)),
|
|
(sra (shl GPR:$b, (i32 16)), (i32 16)))),
|
|
(SMLABB GPR:$a, GPR:$b, GPR:$acc)>;
|
|
def : ARMV5TEPat<(add GPR:$acc,
|
|
(mul sext_16_node:$a, sext_16_node:$b)),
|
|
(SMLABB GPR:$a, GPR:$b, GPR:$acc)>;
|
|
def : ARMV5TEPat<(add GPR:$acc,
|
|
(mul (sra (shl GPR:$a, (i32 16)), (i32 16)),
|
|
(sra GPR:$b, (i32 16)))),
|
|
(SMLABT GPR:$a, GPR:$b, GPR:$acc)>;
|
|
def : ARMV5TEPat<(add GPR:$acc,
|
|
(mul sext_16_node:$a, (sra GPR:$b, (i32 16)))),
|
|
(SMLABT GPR:$a, GPR:$b, GPR:$acc)>;
|
|
def : ARMV5TEPat<(add GPR:$acc,
|
|
(mul (sra GPR:$a, (i32 16)),
|
|
(sra (shl GPR:$b, (i32 16)), (i32 16)))),
|
|
(SMLATB GPR:$a, GPR:$b, GPR:$acc)>;
|
|
def : ARMV5TEPat<(add GPR:$acc,
|
|
(mul (sra GPR:$a, (i32 16)), sext_16_node:$b)),
|
|
(SMLATB GPR:$a, GPR:$b, GPR:$acc)>;
|
|
def : ARMV5TEPat<(add GPR:$acc,
|
|
(sra (mul GPR:$a, (sra (shl GPR:$b, (i32 16)), (i32 16))),
|
|
(i32 16))),
|
|
(SMLAWB GPR:$a, GPR:$b, GPR:$acc)>;
|
|
def : ARMV5TEPat<(add GPR:$acc,
|
|
(sra (mul GPR:$a, sext_16_node:$b), (i32 16))),
|
|
(SMLAWB GPR:$a, GPR:$b, GPR:$acc)>;
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// Thumb Support
|
|
//
|
|
|
|
include "ARMInstrThumb.td"
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// Thumb2 Support
|
|
//
|
|
|
|
include "ARMInstrThumb2.td"
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// Floating Point Support
|
|
//
|
|
|
|
include "ARMInstrVFP.td"
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// Advanced SIMD (NEON) Support
|
|
//
|
|
|
|
include "ARMInstrNEON.td"
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// Coprocessor Instructions. For disassembly only.
|
|
//
|
|
|
|
def CDP : ABI<0b1110, (outs), (ins nohash_imm:$cop, i32imm:$opc1,
|
|
nohash_imm:$CRd, nohash_imm:$CRn, nohash_imm:$CRm, i32imm:$opc2),
|
|
NoItinerary, "cdp", "\tp$cop, $opc1, cr$CRd, cr$CRn, cr$CRm, $opc2",
|
|
[/* For disassembly only; pattern left blank */]> {
|
|
let Inst{4} = 0;
|
|
}
|
|
|
|
def CDP2 : ABXI<0b1110, (outs), (ins nohash_imm:$cop, i32imm:$opc1,
|
|
nohash_imm:$CRd, nohash_imm:$CRn, nohash_imm:$CRm, i32imm:$opc2),
|
|
NoItinerary, "cdp2\tp$cop, $opc1, cr$CRd, cr$CRn, cr$CRm, $opc2",
|
|
[/* For disassembly only; pattern left blank */]> {
|
|
let Inst{31-28} = 0b1111;
|
|
let Inst{4} = 0;
|
|
}
|
|
|
|
class ACI<dag oops, dag iops, string opc, string asm>
|
|
: I<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, BrFrm, NoItinerary,
|
|
opc, asm, "", [/* For disassembly only; pattern left blank */]> {
|
|
let Inst{27-25} = 0b110;
|
|
}
|
|
|
|
multiclass LdStCop<bits<4> op31_28, bit load, string opc> {
|
|
|
|
def _OFFSET : ACI<(outs),
|
|
(ins nohash_imm:$cop, nohash_imm:$CRd, addrmode2:$addr),
|
|
opc, "\tp$cop, cr$CRd, $addr"> {
|
|
let Inst{31-28} = op31_28;
|
|
let Inst{24} = 1; // P = 1
|
|
let Inst{21} = 0; // W = 0
|
|
let Inst{22} = 0; // D = 0
|
|
let Inst{20} = load;
|
|
}
|
|
|
|
def _PRE : ACI<(outs),
|
|
(ins nohash_imm:$cop, nohash_imm:$CRd, addrmode2:$addr),
|
|
opc, "\tp$cop, cr$CRd, $addr!"> {
|
|
let Inst{31-28} = op31_28;
|
|
let Inst{24} = 1; // P = 1
|
|
let Inst{21} = 1; // W = 1
|
|
let Inst{22} = 0; // D = 0
|
|
let Inst{20} = load;
|
|
}
|
|
|
|
def _POST : ACI<(outs),
|
|
(ins nohash_imm:$cop, nohash_imm:$CRd, GPR:$base, am2offset:$offset),
|
|
opc, "\tp$cop, cr$CRd, [$base], $offset"> {
|
|
let Inst{31-28} = op31_28;
|
|
let Inst{24} = 0; // P = 0
|
|
let Inst{21} = 1; // W = 1
|
|
let Inst{22} = 0; // D = 0
|
|
let Inst{20} = load;
|
|
}
|
|
|
|
def _OPTION : ACI<(outs),
|
|
(ins nohash_imm:$cop, nohash_imm:$CRd, GPR:$base, i32imm:$option),
|
|
opc, "\tp$cop, cr$CRd, [$base], $option"> {
|
|
let Inst{31-28} = op31_28;
|
|
let Inst{24} = 0; // P = 0
|
|
let Inst{23} = 1; // U = 1
|
|
let Inst{21} = 0; // W = 0
|
|
let Inst{22} = 0; // D = 0
|
|
let Inst{20} = load;
|
|
}
|
|
|
|
def L_OFFSET : ACI<(outs),
|
|
(ins nohash_imm:$cop, nohash_imm:$CRd, addrmode2:$addr),
|
|
opc, "l\tp$cop, cr$CRd, $addr"> {
|
|
let Inst{31-28} = op31_28;
|
|
let Inst{24} = 1; // P = 1
|
|
let Inst{21} = 0; // W = 0
|
|
let Inst{22} = 1; // D = 1
|
|
let Inst{20} = load;
|
|
}
|
|
|
|
def L_PRE : ACI<(outs),
|
|
(ins nohash_imm:$cop, nohash_imm:$CRd, addrmode2:$addr),
|
|
opc, "l\tp$cop, cr$CRd, $addr!"> {
|
|
let Inst{31-28} = op31_28;
|
|
let Inst{24} = 1; // P = 1
|
|
let Inst{21} = 1; // W = 1
|
|
let Inst{22} = 1; // D = 1
|
|
let Inst{20} = load;
|
|
}
|
|
|
|
def L_POST : ACI<(outs),
|
|
(ins nohash_imm:$cop, nohash_imm:$CRd, GPR:$base, am2offset:$offset),
|
|
opc, "l\tp$cop, cr$CRd, [$base], $offset"> {
|
|
let Inst{31-28} = op31_28;
|
|
let Inst{24} = 0; // P = 0
|
|
let Inst{21} = 1; // W = 1
|
|
let Inst{22} = 1; // D = 1
|
|
let Inst{20} = load;
|
|
}
|
|
|
|
def L_OPTION : ACI<(outs),
|
|
(ins nohash_imm:$cop, nohash_imm:$CRd, GPR:$base, nohash_imm:$option),
|
|
opc, "l\tp$cop, cr$CRd, [$base], $option"> {
|
|
let Inst{31-28} = op31_28;
|
|
let Inst{24} = 0; // P = 0
|
|
let Inst{23} = 1; // U = 1
|
|
let Inst{21} = 0; // W = 0
|
|
let Inst{22} = 1; // D = 1
|
|
let Inst{20} = load;
|
|
}
|
|
}
|
|
|
|
defm LDC : LdStCop<{?,?,?,?}, 1, "ldc">;
|
|
defm LDC2 : LdStCop<0b1111, 1, "ldc2">;
|
|
defm STC : LdStCop<{?,?,?,?}, 0, "stc">;
|
|
defm STC2 : LdStCop<0b1111, 0, "stc2">;
|
|
|
|
def MCR : ABI<0b1110, (outs), (ins nohash_imm:$cop, i32imm:$opc1,
|
|
GPR:$Rt, nohash_imm:$CRn, nohash_imm:$CRm, i32imm:$opc2),
|
|
NoItinerary, "mcr", "\tp$cop, $opc1, $Rt, cr$CRn, cr$CRm, $opc2",
|
|
[/* For disassembly only; pattern left blank */]> {
|
|
let Inst{20} = 0;
|
|
let Inst{4} = 1;
|
|
}
|
|
|
|
def MCR2 : ABXI<0b1110, (outs), (ins nohash_imm:$cop, i32imm:$opc1,
|
|
GPR:$Rt, nohash_imm:$CRn, nohash_imm:$CRm, i32imm:$opc2),
|
|
NoItinerary, "mcr2\tp$cop, $opc1, $Rt, cr$CRn, cr$CRm, $opc2",
|
|
[/* For disassembly only; pattern left blank */]> {
|
|
let Inst{31-28} = 0b1111;
|
|
let Inst{20} = 0;
|
|
let Inst{4} = 1;
|
|
}
|
|
|
|
def MRC : ABI<0b1110, (outs), (ins nohash_imm:$cop, i32imm:$opc1,
|
|
GPR:$Rt, nohash_imm:$CRn, nohash_imm:$CRm, i32imm:$opc2),
|
|
NoItinerary, "mrc", "\tp$cop, $opc1, $Rt, cr$CRn, cr$CRm, $opc2",
|
|
[/* For disassembly only; pattern left blank */]> {
|
|
let Inst{20} = 1;
|
|
let Inst{4} = 1;
|
|
}
|
|
|
|
def MRC2 : ABXI<0b1110, (outs), (ins nohash_imm:$cop, i32imm:$opc1,
|
|
GPR:$Rt, nohash_imm:$CRn, nohash_imm:$CRm, i32imm:$opc2),
|
|
NoItinerary, "mrc2\tp$cop, $opc1, $Rt, cr$CRn, cr$CRm, $opc2",
|
|
[/* For disassembly only; pattern left blank */]> {
|
|
let Inst{31-28} = 0b1111;
|
|
let Inst{20} = 1;
|
|
let Inst{4} = 1;
|
|
}
|
|
|
|
def MCRR : ABI<0b1100, (outs), (ins nohash_imm:$cop, i32imm:$opc,
|
|
GPR:$Rt, GPR:$Rt2, nohash_imm:$CRm),
|
|
NoItinerary, "mcrr", "\tp$cop, $opc, $Rt, $Rt2, cr$CRm",
|
|
[/* For disassembly only; pattern left blank */]> {
|
|
let Inst{23-20} = 0b0100;
|
|
}
|
|
|
|
def MCRR2 : ABXI<0b1100, (outs), (ins nohash_imm:$cop, i32imm:$opc,
|
|
GPR:$Rt, GPR:$Rt2, nohash_imm:$CRm),
|
|
NoItinerary, "mcrr2\tp$cop, $opc, $Rt, $Rt2, cr$CRm",
|
|
[/* For disassembly only; pattern left blank */]> {
|
|
let Inst{31-28} = 0b1111;
|
|
let Inst{23-20} = 0b0100;
|
|
}
|
|
|
|
def MRRC : ABI<0b1100, (outs), (ins nohash_imm:$cop, i32imm:$opc,
|
|
GPR:$Rt, GPR:$Rt2, nohash_imm:$CRm),
|
|
NoItinerary, "mrrc", "\tp$cop, $opc, $Rt, $Rt2, cr$CRm",
|
|
[/* For disassembly only; pattern left blank */]> {
|
|
let Inst{23-20} = 0b0101;
|
|
}
|
|
|
|
def MRRC2 : ABXI<0b1100, (outs), (ins nohash_imm:$cop, i32imm:$opc,
|
|
GPR:$Rt, GPR:$Rt2, nohash_imm:$CRm),
|
|
NoItinerary, "mrrc2\tp$cop, $opc, $Rt, $Rt2, cr$CRm",
|
|
[/* For disassembly only; pattern left blank */]> {
|
|
let Inst{31-28} = 0b1111;
|
|
let Inst{23-20} = 0b0101;
|
|
}
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// Move between special register and ARM core register -- for disassembly only
|
|
//
|
|
|
|
def MRS : ABI<0b0001,(outs GPR:$dst),(ins), NoItinerary, "mrs", "\t$dst, cpsr",
|
|
[/* For disassembly only; pattern left blank */]> {
|
|
let Inst{23-20} = 0b0000;
|
|
let Inst{7-4} = 0b0000;
|
|
}
|
|
|
|
def MRSsys : ABI<0b0001,(outs GPR:$dst),(ins), NoItinerary,"mrs","\t$dst, spsr",
|
|
[/* For disassembly only; pattern left blank */]> {
|
|
let Inst{23-20} = 0b0100;
|
|
let Inst{7-4} = 0b0000;
|
|
}
|
|
|
|
def MSR : ABI<0b0001, (outs), (ins GPR:$src, msr_mask:$mask), NoItinerary,
|
|
"msr", "\tcpsr$mask, $src",
|
|
[/* For disassembly only; pattern left blank */]> {
|
|
let Inst{23-20} = 0b0010;
|
|
let Inst{7-4} = 0b0000;
|
|
}
|
|
|
|
def MSRi : ABI<0b0011, (outs), (ins so_imm:$a, msr_mask:$mask), NoItinerary,
|
|
"msr", "\tcpsr$mask, $a",
|
|
[/* For disassembly only; pattern left blank */]> {
|
|
let Inst{23-20} = 0b0010;
|
|
let Inst{7-4} = 0b0000;
|
|
}
|
|
|
|
def MSRsys : ABI<0b0001, (outs), (ins GPR:$src, msr_mask:$mask), NoItinerary,
|
|
"msr", "\tspsr$mask, $src",
|
|
[/* For disassembly only; pattern left blank */]> {
|
|
let Inst{23-20} = 0b0110;
|
|
let Inst{7-4} = 0b0000;
|
|
}
|
|
|
|
def MSRsysi : ABI<0b0011, (outs), (ins so_imm:$a, msr_mask:$mask), NoItinerary,
|
|
"msr", "\tspsr$mask, $a",
|
|
[/* For disassembly only; pattern left blank */]> {
|
|
let Inst{23-20} = 0b0110;
|
|
let Inst{7-4} = 0b0000;
|
|
}
|