llvm-6502/lib/Target/Sparc
2012-10-18 23:22:48 +00:00
..
MCTargetDesc
TargetInfo
CMakeLists.txt llvm/lib: [CMake] Add explicit dependency to intrinsics_gen. 2012-06-24 13:32:01 +00:00
DelaySlotFiller.cpp Switch some getAliasSet clients to MCRegAliasIterator. 2012-06-01 20:36:54 +00:00
FPMover.cpp
LLVMBuild.txt
Makefile
README.txt
Sparc.h
Sparc.td
SparcAsmPrinter.cpp There are a number of generic inline asm operand modifiers that 2012-06-26 13:49:27 +00:00
SparcCallingConv.td
SparcFrameLowering.cpp Move TargetData to DataLayout. 2012-10-08 16:38:25 +00:00
SparcFrameLowering.h Round 2 of dead private variable removal. 2012-06-06 19:47:08 +00:00
SparcInstrFormats.td
SparcInstrInfo.cpp
SparcInstrInfo.h
SparcInstrInfo.td Add missing SDNP properties on the flushw node. 2012-08-24 00:31:13 +00:00
SparcISelDAGToDAG.cpp
SparcISelLowering.cpp Move TargetData to DataLayout. 2012-10-08 16:38:25 +00:00
SparcISelLowering.h Change interface for TargetLowering::LowerCallTo and TargetLowering::LowerCall 2012-05-25 16:35:28 +00:00
SparcMachineFunctionInfo.cpp
SparcMachineFunctionInfo.h
SparcRegisterInfo.cpp Remove empty overrides of processFunctionBeforeFrameFinalized(). 2012-08-06 18:14:18 +00:00
SparcRegisterInfo.h
SparcRegisterInfo.td
SparcSelectionDAGInfo.cpp
SparcSelectionDAGInfo.h
SparcSubtarget.cpp
SparcSubtarget.h
SparcTargetMachine.cpp Reapply the TargerTransformInfo changes, minus the changes to LSR and Lowerinvoke. 2012-10-18 23:22:48 +00:00
SparcTargetMachine.h Reapply the TargerTransformInfo changes, minus the changes to LSR and Lowerinvoke. 2012-10-18 23:22:48 +00:00

To-do
-----

* Keep the address of the constant pool in a register instead of forming its
  address all of the time.
* We can fold small constant offsets into the %hi/%lo references to constant
  pool addresses as well.
* When in V9 mode, register allocate %icc[0-3].
* Add support for isel'ing UMUL_LOHI instead of marking it as Expand.
* Emit the 'Branch on Integer Register with Prediction' instructions.  It's
  not clear how to write a pattern for this though:

float %t1(int %a, int* %p) {
        %C = seteq int %a, 0
        br bool %C, label %T, label %F
T:
        store int 123, int* %p
        br label %F
F:
        ret float undef
}

codegens to this:

t1:
        save -96, %o6, %o6
1)      subcc %i0, 0, %l0
1)      bne .LBBt1_2    ! F
        nop
.LBBt1_1:       ! T
        or %g0, 123, %l0
        st %l0, [%i1]
.LBBt1_2:       ! F
        restore %g0, %g0, %g0
        retl
        nop

1) should be replaced with a brz in V9 mode.

* Same as above, but emit conditional move on register zero (p192) in V9 
  mode.  Testcase:

int %t1(int %a, int %b) {
        %C = seteq int %a, 0
        %D = select bool %C, int %a, int %b
        ret int %D
}

* Emit MULX/[SU]DIVX instructions in V9 mode instead of fiddling 
  with the Y register, if they are faster.

* Codegen bswap(load)/store(bswap) -> load/store ASI

* Implement frame pointer elimination, e.g. eliminate save/restore for 
  leaf fns.
* Fill delay slots

* Implement JIT support