llvm-6502/test/CodeGen
Andrea Di Biagio 817812f61c [X86] Improve the selection of SSE3/AVX addsub instructions.
This patch teaches the backend how to canonicalize a shuffle vectors
according to the rule:

 - (shuffle (FADD A, B), (FSUB A, B), Mask) ->
       (shuffle (FSUB A, -B), (FADD A, -B), Mask)

Where 'Mask' is:
  <0,5,2,7>            ;; for v4f32 and v4f64 shuffles.
  <0,3>                ;; for v2f64 shuffles.
  <0,9,2,11,4,13,6,15> ;; for v8f32 shuffles.

In general, ISel only knows how to pattern-match a canonical
'fadd + fsub + blendi' dag node sequence into an ADDSUB instruction.

This new rule allows to convert a non-canonical dag sequence into a
canonical one that will be matched by a single ADDSUB at ISel stage.

The idea of converting a non-canonical ADDSUB into a canonical one by
swapping the first two operands of the shuffle, and then negating the
second operand of the FADD and FSUB, was originally proposed by Hal Finkel.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211771 91177308-0d34-0410-b5e6-96231b3b80d8
2014-06-26 10:45:21 +00:00
..
AArch64 Resubmit commit r211533 2014-06-24 16:21:38 +00:00
ARM Fix up scoping in a few tests (and delete one that validates unnecessary behavior). 2014-06-24 20:10:27 +00:00
CPP
Generic
Hexagon
Inputs
Mips Print a=b as an assignment. 2014-06-24 22:45:16 +00:00
MSP430
NVPTX
PowerPC Rename loop unrolling and loop vectorizer metadata to have a common prefix. 2014-06-25 15:41:00 +00:00
R600 R600: Fix vector FMA 2014-06-26 01:28:05 +00:00
SPARC
SystemZ
Thumb
Thumb2 ARM: Fix TPsoft for Thumb mode 2014-06-24 15:45:59 +00:00
X86 [X86] Improve the selection of SSE3/AVX addsub instructions. 2014-06-26 10:45:21 +00:00
XCore