llvm-6502/lib/CodeGen
Duncan Sands edfcf598fa Sometimes (rarely) nodes held in LegalizeTypes
maps can be deleted.  This happens when RAUW
replaces a node N with another equivalent node
E, deleting the first node.  Solve this by
adding (N, E) to ReplacedNodes, which is already
used to remap nodes to replacements.  This means
that deleted nodes are being allowed in maps,
which can be delicate: the memory may be reused
for a new node which might get confused with the
old deleted node pointer hanging around in the
maps, so detect this and flush out maps if it
occurs (ExpungeNode).  The expunging operation
is expensive, however it never occurs during
a llvm-gcc bootstrap or anywhere in the nightly
testsuite.  It occurs three times in "make check":
Alpha/illegal-element-type.ll,
PowerPC/illegal-element-type.ll and
X86/mmx-shift.ll.  If expunging proves to be too
expensive then there are other more complicated
ways of solving the problem.
In the normal case this patch adds the overhead
of a few more map lookups, which is hopefully
negligable.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@52214 91177308-0d34-0410-b5e6-96231b3b80d8
2008-06-11 11:42:12 +00:00
..
SelectionDAG Sometimes (rarely) nodes held in LegalizeTypes 2008-06-11 11:42:12 +00:00
AsmPrinter.cpp Change packed struct layout so that field sizes 2008-06-04 08:21:45 +00:00
BranchFolding.cpp Rewrite a loop to avoid using iterators pointing to 2008-05-23 17:19:02 +00:00
Collector.cpp Turn StripPointerCast() into a method 2008-05-07 22:54:15 +00:00
CollectorMetadata.cpp Clean up the use of static and anonymous namespaces. This turned up 2008-05-13 00:00:25 +00:00
Collectors.cpp Remove attribution from file headers, per discussion on llvmdev. 2007-12-29 20:36:04 +00:00
DwarfWriter.cpp Get exception handling working again on 64 bit 2008-05-08 12:33:11 +00:00
ELFWriter.cpp Add CommonLinkage; currently tentative definitions 2008-05-14 20:12:51 +00:00
ELFWriter.h Don't include <map> in Pass.h, which doesn't need it. This requires 2008-03-21 23:51:57 +00:00
IfConversion.cpp Register if-converter pass for -debug-pass. 2008-06-04 09:15:51 +00:00
IntrinsicLowering.cpp API change for {BinaryOperator|CmpInst|CastInst}::create*() --> Create. Legacy interfaces will be in place for some time. (Merge from use-diet branch.) 2008-05-16 19:29:10 +00:00
LiveInterval.cpp Add a stack slot coloring pass. Not yet enabled. 2008-06-04 09:18:41 +00:00
LiveIntervalAnalysis.cpp Refine stack slot interval weight computation. 2008-06-06 07:54:39 +00:00
LiveStackAnalysis.cpp Add a stack slot coloring pass. Not yet enabled. 2008-06-04 09:18:41 +00:00
LiveVariables.cpp Rewrite LiveVariable liveness computation. The new implementation is much simplified. It eliminated the nasty recursive routines and removed the partial def / use bookkeeping. There is also potential for performance improvement by replacing the conservative handling of partial physical register definitions. The code is currently disabled until live interval analysis is taught of the name scheme. 2008-04-16 09:46:40 +00:00
LLVMTargetMachine.cpp Enable stack coloring by default. 2008-06-06 19:52:44 +00:00
LoopAligner.cpp Fix PR2112: don't run loop aligner if target doesn't have a TargetLowering object. 2008-02-29 17:52:15 +00:00
LowerSubregs.cpp Revert this. 2008-06-04 17:21:44 +00:00
MachineBasicBlock.cpp Added addition atomic instrinsics and, or, xor, min, and max. 2008-05-05 19:05:59 +00:00
MachineDominators.cpp Change class' public PassInfo variables to by initialized with the 2008-05-13 02:05:11 +00:00
MachineFunction.cpp Silence warning when no assertions. 2008-04-06 21:46:45 +00:00
MachineInstr.cpp Add a flag to indicate that an instruction is as cheap (or cheaper) than a move 2008-05-28 22:54:52 +00:00
MachineLICM.cpp Clean up the use of static and anonymous namespaces. This turned up 2008-05-13 00:00:25 +00:00
MachineLoopInfo.cpp Change class' public PassInfo variables to by initialized with the 2008-05-13 02:05:11 +00:00
MachineModuleInfo.cpp Clean up the use of static and anonymous namespaces. This turned up 2008-05-13 00:00:25 +00:00
MachinePassRegistry.cpp Remove attribution from file headers, per discussion on llvmdev. 2007-12-29 20:36:04 +00:00
MachineRegisterInfo.cpp Added debugging routine dumpUses. 2008-02-13 02:45:38 +00:00
MachineSink.cpp Clean up the use of static and anonymous namespaces. This turned up 2008-05-13 00:00:25 +00:00
MachOWriter.cpp Use isSingleValueType instead of isFirstClassType to 2008-05-23 00:17:26 +00:00
MachOWriter.h Don't include <map> in Pass.h, which doesn't need it. This requires 2008-03-21 23:51:57 +00:00
Makefile remove attribution from lib Makefiles. 2007-12-29 20:09:26 +00:00
OcamlCollector.cpp Clean up the use of static and anonymous namespaces. This turned up 2008-05-13 00:00:25 +00:00
Passes.cpp Clean up the use of static and anonymous namespaces. This turned up 2008-05-13 00:00:25 +00:00
PHIElimination.cpp Change class' public PassInfo variables to by initialized with the 2008-05-13 02:05:11 +00:00
PhysRegTracker.h Rename MRegisterInfo to TargetRegisterInfo. 2008-02-10 18:45:23 +00:00
PostRASchedulerList.cpp don't create the post-ra scheduler unless it is enabled. 2008-01-14 19:00:06 +00:00
PrologEpilogInserter.cpp Fixed bug in bad behavior in calculateFrameObjectOffsets, 2008-06-03 08:46:59 +00:00
PseudoSourceValue.cpp A quick nm audit turned up several fixed tables and objects that were 2008-03-25 21:45:14 +00:00
README.txt Enable stack coloring by default. 2008-06-06 19:52:44 +00:00
RegAllocBigBlock.cpp Clean up the use of static and anonymous namespaces. This turned up 2008-05-13 00:00:25 +00:00
RegAllocLinearScan.cpp Refine stack slot interval weight computation. 2008-06-06 07:54:39 +00:00
RegAllocLocal.cpp Teach local register allocator to deal with landing pad MBB's. 2008-05-28 17:22:32 +00:00
RegAllocSimple.cpp Don't include <map> in Pass.h, which doesn't need it. This requires 2008-03-21 23:51:57 +00:00
RegisterCoalescer.cpp Clean up the use of static and anonymous namespaces. This turned up 2008-05-13 00:00:25 +00:00
RegisterScavenging.cpp Fix some constructs that gcc-4.4 warns about. 2008-05-27 11:50:51 +00:00
ShadowStackCollector.cpp Clean up the use of static and anonymous namespaces. This turned up 2008-05-13 00:00:25 +00:00
SimpleRegisterCoalescing.cpp The coalescer doesn't need LiveVariables now that we have register use iterators. 2008-05-30 22:37:27 +00:00
SimpleRegisterCoalescing.h The coalescer doesn't need LiveVariables now that we have register use iterators. 2008-05-30 22:37:27 +00:00
StackSlotColoring.cpp Add a stack slot coloring pass. Not yet enabled. 2008-06-04 09:18:41 +00:00
StrongPHIElimination.cpp Remove debugging code. 2008-06-05 18:43:34 +00:00
TargetInstrInfoImpl.cpp Infrastructure for getting the machine code size of a function and an instruction. X86, PowerPC and ARM are implemented 2008-04-16 20:10:13 +00:00
TwoAddressInstructionPass.cpp Implement "AsCheapAsAMove" for some obviously cheap instructions: xor and the 2008-05-29 01:02:09 +00:00
UnreachableBlockElim.cpp Clean up the use of static and anonymous namespaces. This turned up 2008-05-13 00:00:25 +00:00
VirtRegMap.cpp Move #include to right place. 2008-06-04 09:16:33 +00:00
VirtRegMap.h Move #include to right place. 2008-06-04 09:16:33 +00:00

//===---------------------------------------------------------------------===//

Common register allocation / spilling problem:

        mul lr, r4, lr
        str lr, [sp, #+52]
        ldr lr, [r1, #+32]
        sxth r3, r3
        ldr r4, [sp, #+52]
        mla r4, r3, lr, r4

can be:

        mul lr, r4, lr
        mov r4, lr
        str lr, [sp, #+52]
        ldr lr, [r1, #+32]
        sxth r3, r3
        mla r4, r3, lr, r4

and then "merge" mul and mov:

        mul r4, r4, lr
        str lr, [sp, #+52]
        ldr lr, [r1, #+32]
        sxth r3, r3
        mla r4, r3, lr, r4

It also increase the likelyhood the store may become dead.

//===---------------------------------------------------------------------===//

I think we should have a "hasSideEffects" flag (which is automatically set for
stuff that "isLoad" "isCall" etc), and the remat pass should eventually be able
to remat any instruction that has no side effects, if it can handle it and if
profitable.

For now, I'd suggest having the remat stuff work like this:

1. I need to spill/reload this thing.
2. Check to see if it has side effects.
3. Check to see if it is simple enough: e.g. it only has one register
destination and no register input.
4. If so, clone the instruction, do the xform, etc.

Advantages of this are:

1. the .td file describes the behavior of the instructions, not the way the
   algorithm should work.
2. as remat gets smarter in the future, we shouldn't have to be changing the .td
   files.
3. it is easier to explain what the flag means in the .td file, because you
   don't have to pull in the explanation of how the current remat algo works.

Some potential added complexities:

1. Some instructions have to be glued to it's predecessor or successor. All of
   the PC relative instructions and condition code setting instruction. We could
   mark them as hasSideEffects, but that's not quite right. PC relative loads
   from constantpools can be remat'ed, for example. But it requires more than
   just cloning the instruction. Some instructions can be remat'ed but it
   expands to more than one instruction. But allocator will have to make a
   decision.

4. As stated in 3, not as simple as cloning in some cases. The target will have
   to decide how to remat it. For example, an ARM 2-piece constant generation
   instruction is remat'ed as a load from constantpool.

//===---------------------------------------------------------------------===//

bb27 ...
        ...
        %reg1037 = ADDri %reg1039, 1
        %reg1038 = ADDrs %reg1032, %reg1039, %NOREG, 10
    Successors according to CFG: 0x8b03bf0 (#5)

bb76 (0x8b03bf0, LLVM BB @0x8b032d0, ID#5):
    Predecessors according to CFG: 0x8b0c5f0 (#3) 0x8b0a7c0 (#4)
        %reg1039 = PHI %reg1070, mbb<bb76.outer,0x8b0c5f0>, %reg1037, mbb<bb27,0x8b0a7c0>

Note ADDri is not a two-address instruction. However, its result %reg1037 is an
operand of the PHI node in bb76 and its operand %reg1039 is the result of the
PHI node. We should treat it as a two-address code and make sure the ADDri is
scheduled after any node that reads %reg1039.

//===---------------------------------------------------------------------===//

Use local info (i.e. register scavenger) to assign it a free register to allow
reuse:
	ldr r3, [sp, #+4]
	add r3, r3, #3
	ldr r2, [sp, #+8]
	add r2, r2, #2
	ldr r1, [sp, #+4]  <==
	add r1, r1, #1
	ldr r0, [sp, #+4]
	add r0, r0, #2

//===---------------------------------------------------------------------===//

LLVM aggressively lift CSE out of loop. Sometimes this can be negative side-
effects:

R1 = X + 4
R2 = X + 7
R3 = X + 15

loop:
load [i + R1]
...
load [i + R2]
...
load [i + R3]

Suppose there is high register pressure, R1, R2, R3, can be spilled. We need
to implement proper re-materialization to handle this:

R1 = X + 4
R2 = X + 7
R3 = X + 15

loop:
R1 = X + 4  @ re-materialized
load [i + R1]
...
R2 = X + 7 @ re-materialized
load [i + R2]
...
R3 = X + 15 @ re-materialized
load [i + R3]

Furthermore, with re-association, we can enable sharing:

R1 = X + 4
R2 = X + 7
R3 = X + 15

loop:
T = i + X
load [T + 4]
...
load [T + 7]
...
load [T + 15]
//===---------------------------------------------------------------------===//

It's not always a good idea to choose rematerialization over spilling. If all
the load / store instructions would be folded then spilling is cheaper because
it won't require new live intervals / registers. See 2003-05-31-LongShifts for
an example.

//===---------------------------------------------------------------------===//

With a copying garbage collector, derived pointers must not be retained across
collector safe points; the collector could move the objects and invalidate the
derived pointer. This is bad enough in the first place, but safe points can
crop up unpredictably. Consider:

        %array = load { i32, [0 x %obj] }** %array_addr
        %nth_el = getelementptr { i32, [0 x %obj] }* %array, i32 0, i32 %n
        %old = load %obj** %nth_el
        %z = div i64 %x, %y
        store %obj* %new, %obj** %nth_el

If the i64 division is lowered to a libcall, then a safe point will (must)
appear for the call site. If a collection occurs, %array and %nth_el no longer
point into the correct object.

The fix for this is to copy address calculations so that dependent pointers
are never live across safe point boundaries. But the loads cannot be copied
like this if there was an intervening store, so may be hard to get right.

Only a concurrent mutator can trigger a collection at the libcall safe point.
So single-threaded programs do not have this requirement, even with a copying
collector. Still, LLVM optimizations would probably undo a front-end's careful
work.

//===---------------------------------------------------------------------===//

The ocaml frametable structure supports liveness information. It would be good
to support it.

//===---------------------------------------------------------------------===//

The FIXME in ComputeCommonTailLength in BranchFolding.cpp needs to be
revisited. The check is there to work around a misuse of directives in inline
assembly.

//===---------------------------------------------------------------------===//

It would be good to detect collector/target compatibility instead of silently
doing the wrong thing.

//===---------------------------------------------------------------------===//

It would be really nice to be able to write patterns in .td files for copies,
which would eliminate a bunch of explicit predicates on them (e.g. no side 
effects).  Once this is in place, it would be even better to have tblgen 
synthesize the various copy insertion/inspection methods in TargetInstrInfo.

//===---------------------------------------------------------------------===//

Stack coloring improvments:

1. Do proper LiveStackAnalysis on all stack objects including those which are
   not spill slots.
2. Reorder objects to fill in gaps between objects.
   e.g. 4, 1, <gap>, 4, 1, 1, 1, <gap>, 4 => 4, 1, 1, 1, 1, 4, 4