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https://github.com/c64scene-ar/llvm-6502.git
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1693e489e6
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29194 91177308-0d34-0410-b5e6-96231b3b80d8
98 lines
4.7 KiB
C++
98 lines
4.7 KiB
C++
//====- X86InstrMMX.td - Describe the X86 Instruction Set -------*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file was developed by the Evan Cheng and is distributed under
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// the University of Illinois Open Source License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file describes the X86 MMX instruction set, defining the instructions,
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// and properties of the instructions which are needed for code generation,
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// machine code emission, and analysis.
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//
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//===----------------------------------------------------------------------===//
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// Instruction templates
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// MMXI - MMX instructions with TB prefix.
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// MMX2I - MMX / SSE2 instructions with TB and OpSize prefixes.
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// MMXIi8 - MMX instructions with ImmT == Imm8 and TB prefix.
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class MMXI<bits<8> o, Format F, dag ops, string asm, list<dag> pattern>
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: I<o, F, ops, asm, pattern>, TB, Requires<[HasMMX]>;
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class MMX2I<bits<8> o, Format F, dag ops, string asm, list<dag> pattern>
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: I<o, F, ops, asm, pattern>, TB, OpSize, Requires<[HasSSE2]>;
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class MMXIi8<bits<8> o, Format F, dag ops, string asm, list<dag> pattern>
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: Ii8<o, F, ops, asm, pattern>, TB, Requires<[HasMMX]>;
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// Some 'special' instructions
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def IMPLICIT_DEF_VR64 : I<0, Pseudo, (ops VR64:$dst),
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"#IMPLICIT_DEF $dst",
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[(set VR64:$dst, (v8i8 (undef)))]>,
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Requires<[HasMMX]>;
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def : Pat<(v4i16 (undef)), (IMPLICIT_DEF_VR64)>, Requires<[HasMMX]>;
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def : Pat<(v2i32 (undef)), (IMPLICIT_DEF_VR64)>, Requires<[HasMMX]>;
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// Move Instructions
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def MOVD64rr : I<0x6E, MRMSrcReg, (ops VR64:$dst, GR32:$src),
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"movd {$src, $dst|$dst, $src}", []>, TB,
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Requires<[HasMMX]>;
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def MOVD64rm : I<0x6E, MRMSrcMem, (ops VR64:$dst, i32mem:$src),
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"movd {$src, $dst|$dst, $src}", []>, TB,
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Requires<[HasMMX]>;
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def MOVD64mr : I<0x7E, MRMDestMem, (ops i32mem:$dst, VR64:$src),
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"movd {$src, $dst|$dst, $src}", []>, TB,
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Requires<[HasMMX]>;
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def MOVQ64rr : I<0x6F, MRMSrcReg, (ops VR64:$dst, VR64:$src),
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"movq {$src, $dst|$dst, $src}", []>, TB,
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Requires<[HasMMX]>;
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def MOVQ64rm : I<0x6F, MRMSrcMem, (ops VR64:$dst, i64mem:$src),
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"movq {$src, $dst|$dst, $src}", []>, TB,
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Requires<[HasMMX]>;
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def MOVQ64mr : I<0x7F, MRMDestMem, (ops i64mem:$dst, VR64:$src),
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"movq {$src, $dst|$dst, $src}", []>, TB,
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Requires<[HasMMX]>;
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// Conversion instructions
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def CVTPI2PSrr : MMXI<0x2A, MRMSrcReg, (ops VR128:$dst, VR64:$src),
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"cvtpi2ps {$src, $dst|$dst, $src}", []>;
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def CVTPI2PSrm : MMXI<0x2A, MRMSrcMem, (ops VR128:$dst, i64mem:$src),
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"cvtpi2ps {$src, $dst|$dst, $src}", []>;
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def CVTPI2PDrr : MMX2I<0x2A, MRMSrcReg, (ops VR128:$dst, VR64:$src),
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"cvtpi2pd {$src, $dst|$dst, $src}", []>;
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def CVTPI2PDrm : MMX2I<0x2A, MRMSrcMem, (ops VR128:$dst, i64mem:$src),
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"cvtpi2pd {$src, $dst|$dst, $src}", []>;
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def CVTTPS2PIrr: I<0x2C, MRMSrcReg, (ops VR64:$dst, VR128:$src),
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"cvttps2pi {$src, $dst|$dst, $src}", []>, TB,
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Requires<[HasSSE2]>;
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def CVTTPS2PIrm: I<0x2C, MRMSrcMem, (ops VR64:$dst, f64mem:$src),
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"cvttps2pi {$src, $dst|$dst, $src}", []>, TB,
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Requires<[HasMMX]>;
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def CVTPS2PIrr : MMXI<0x2D, MRMSrcReg, (ops VR64:$dst, VR128:$src),
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"cvtps2pi {$src, $dst|$dst, $src}", []>;
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def CVTPS2PIrm : MMXI<0x2D, MRMSrcMem, (ops VR64:$dst, f64mem:$src),
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"cvtps2pi {$src, $dst|$dst, $src}", []>;
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def CVTPD2PIrr : MMX2I<0x2D, MRMSrcReg, (ops VR64:$dst, VR128:$src),
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"cvtpd2pi {$src, $dst|$dst, $src}", []>;
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def CVTPD2PIrm : MMX2I<0x2D, MRMSrcMem, (ops VR64:$dst, f128mem:$src),
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"cvtpd2pi {$src, $dst|$dst, $src}", []>;
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// Shuffle and unpack instructions
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def PSHUFWri : MMXIi8<0x70, MRMSrcReg,
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(ops VR64:$dst, VR64:$src1, i8imm:$src2),
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"pshufw {$src2, $src1, $dst|$dst, $src1, $src2}", []>;
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def PSHUFWmi : MMXIi8<0x70, MRMSrcMem,
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(ops VR64:$dst, i64mem:$src1, i8imm:$src2),
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"pshufw {$src2, $src1, $dst|$dst, $src1, $src2}", []>;
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// Misc.
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def MOVNTQ : I<0xE7, MRMDestMem, (ops i64mem:$dst, VR64:$src),
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"movntq {$src, $dst|$dst, $src}", []>, TB,
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Requires<[HasMMX]>;
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def MASKMOVQ : I<0xF7, MRMDestMem, (ops VR64:$src, VR64:$mask),
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"maskmovq {$mask, $src|$src, $mask}", []>, TB,
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Requires<[HasMMX]>;
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