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https://github.com/c64scene-ar/llvm-6502.git
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135930 91177308-0d34-0410-b5e6-96231b3b80d8
545 lines
20 KiB
C++
545 lines
20 KiB
C++
//===-- X86BaseInfo.h - Top level definitions for X86 -------- --*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains small standalone helper functions and enum definitions for
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// the X86 target useful for the compiler back-end and the MC libraries.
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// As such, it deliberately does not include references to LLVM core
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// code gen types, passes, etc..
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//
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//===----------------------------------------------------------------------===//
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#ifndef X86BASEINFO_H
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#define X86BASEINFO_H
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#include "X86MCTargetDesc.h"
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#include "llvm/Support/DataTypes.h"
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#include <cassert>
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namespace llvm {
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namespace X86 {
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// Enums for memory operand decoding. Each memory operand is represented with
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// a 5 operand sequence in the form:
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// [BaseReg, ScaleAmt, IndexReg, Disp, Segment]
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// These enums help decode this.
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enum {
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AddrBaseReg = 0,
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AddrScaleAmt = 1,
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AddrIndexReg = 2,
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AddrDisp = 3,
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/// AddrSegmentReg - The operand # of the segment in the memory operand.
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AddrSegmentReg = 4,
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/// AddrNumOperands - Total number of operands in a memory reference.
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AddrNumOperands = 5
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};
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} // end namespace X86;
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/// X86II - This namespace holds all of the target specific flags that
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/// instruction info tracks.
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///
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namespace X86II {
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/// Target Operand Flag enum.
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enum TOF {
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//===------------------------------------------------------------------===//
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// X86 Specific MachineOperand flags.
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MO_NO_FLAG,
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/// MO_GOT_ABSOLUTE_ADDRESS - On a symbol operand, this represents a
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/// relocation of:
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/// SYMBOL_LABEL + [. - PICBASELABEL]
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MO_GOT_ABSOLUTE_ADDRESS,
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/// MO_PIC_BASE_OFFSET - On a symbol operand this indicates that the
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/// immediate should get the value of the symbol minus the PIC base label:
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/// SYMBOL_LABEL - PICBASELABEL
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MO_PIC_BASE_OFFSET,
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/// MO_GOT - On a symbol operand this indicates that the immediate is the
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/// offset to the GOT entry for the symbol name from the base of the GOT.
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///
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/// See the X86-64 ELF ABI supplement for more details.
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/// SYMBOL_LABEL @GOT
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MO_GOT,
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/// MO_GOTOFF - On a symbol operand this indicates that the immediate is
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/// the offset to the location of the symbol name from the base of the GOT.
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///
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/// See the X86-64 ELF ABI supplement for more details.
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/// SYMBOL_LABEL @GOTOFF
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MO_GOTOFF,
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/// MO_GOTPCREL - On a symbol operand this indicates that the immediate is
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/// offset to the GOT entry for the symbol name from the current code
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/// location.
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///
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/// See the X86-64 ELF ABI supplement for more details.
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/// SYMBOL_LABEL @GOTPCREL
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MO_GOTPCREL,
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/// MO_PLT - On a symbol operand this indicates that the immediate is
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/// offset to the PLT entry of symbol name from the current code location.
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///
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/// See the X86-64 ELF ABI supplement for more details.
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/// SYMBOL_LABEL @PLT
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MO_PLT,
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/// MO_TLSGD - On a symbol operand this indicates that the immediate is
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/// some TLS offset.
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///
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/// See 'ELF Handling for Thread-Local Storage' for more details.
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/// SYMBOL_LABEL @TLSGD
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MO_TLSGD,
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/// MO_GOTTPOFF - On a symbol operand this indicates that the immediate is
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/// some TLS offset.
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///
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/// See 'ELF Handling for Thread-Local Storage' for more details.
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/// SYMBOL_LABEL @GOTTPOFF
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MO_GOTTPOFF,
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/// MO_INDNTPOFF - On a symbol operand this indicates that the immediate is
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/// some TLS offset.
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///
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/// See 'ELF Handling for Thread-Local Storage' for more details.
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/// SYMBOL_LABEL @INDNTPOFF
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MO_INDNTPOFF,
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/// MO_TPOFF - On a symbol operand this indicates that the immediate is
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/// some TLS offset.
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///
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/// See 'ELF Handling for Thread-Local Storage' for more details.
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/// SYMBOL_LABEL @TPOFF
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MO_TPOFF,
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/// MO_NTPOFF - On a symbol operand this indicates that the immediate is
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/// some TLS offset.
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///
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/// See 'ELF Handling for Thread-Local Storage' for more details.
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/// SYMBOL_LABEL @NTPOFF
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MO_NTPOFF,
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/// MO_DLLIMPORT - On a symbol operand "FOO", this indicates that the
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/// reference is actually to the "__imp_FOO" symbol. This is used for
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/// dllimport linkage on windows.
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MO_DLLIMPORT,
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/// MO_DARWIN_STUB - On a symbol operand "FOO", this indicates that the
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/// reference is actually to the "FOO$stub" symbol. This is used for calls
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/// and jumps to external functions on Tiger and earlier.
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MO_DARWIN_STUB,
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/// MO_DARWIN_NONLAZY - On a symbol operand "FOO", this indicates that the
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/// reference is actually to the "FOO$non_lazy_ptr" symbol, which is a
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/// non-PIC-base-relative reference to a non-hidden dyld lazy pointer stub.
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MO_DARWIN_NONLAZY,
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/// MO_DARWIN_NONLAZY_PIC_BASE - On a symbol operand "FOO", this indicates
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/// that the reference is actually to "FOO$non_lazy_ptr - PICBASE", which is
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/// a PIC-base-relative reference to a non-hidden dyld lazy pointer stub.
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MO_DARWIN_NONLAZY_PIC_BASE,
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/// MO_DARWIN_HIDDEN_NONLAZY_PIC_BASE - On a symbol operand "FOO", this
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/// indicates that the reference is actually to "FOO$non_lazy_ptr -PICBASE",
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/// which is a PIC-base-relative reference to a hidden dyld lazy pointer
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/// stub.
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MO_DARWIN_HIDDEN_NONLAZY_PIC_BASE,
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/// MO_TLVP - On a symbol operand this indicates that the immediate is
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/// some TLS offset.
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///
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/// This is the TLS offset for the Darwin TLS mechanism.
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MO_TLVP,
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/// MO_TLVP_PIC_BASE - On a symbol operand this indicates that the immediate
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/// is some TLS offset from the picbase.
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///
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/// This is the 32-bit TLS offset for Darwin TLS in PIC mode.
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MO_TLVP_PIC_BASE
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};
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enum {
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//===------------------------------------------------------------------===//
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// Instruction encodings. These are the standard/most common forms for X86
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// instructions.
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//
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// PseudoFrm - This represents an instruction that is a pseudo instruction
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// or one that has not been implemented yet. It is illegal to code generate
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// it, but tolerated for intermediate implementation stages.
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Pseudo = 0,
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/// Raw - This form is for instructions that don't have any operands, so
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/// they are just a fixed opcode value, like 'leave'.
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RawFrm = 1,
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/// AddRegFrm - This form is used for instructions like 'push r32' that have
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/// their one register operand added to their opcode.
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AddRegFrm = 2,
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/// MRMDestReg - This form is used for instructions that use the Mod/RM byte
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/// to specify a destination, which in this case is a register.
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///
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MRMDestReg = 3,
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/// MRMDestMem - This form is used for instructions that use the Mod/RM byte
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/// to specify a destination, which in this case is memory.
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///
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MRMDestMem = 4,
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/// MRMSrcReg - This form is used for instructions that use the Mod/RM byte
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/// to specify a source, which in this case is a register.
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///
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MRMSrcReg = 5,
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/// MRMSrcMem - This form is used for instructions that use the Mod/RM byte
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/// to specify a source, which in this case is memory.
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///
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MRMSrcMem = 6,
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/// MRM[0-7][rm] - These forms are used to represent instructions that use
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/// a Mod/RM byte, and use the middle field to hold extended opcode
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/// information. In the intel manual these are represented as /0, /1, ...
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///
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// First, instructions that operate on a register r/m operand...
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MRM0r = 16, MRM1r = 17, MRM2r = 18, MRM3r = 19, // Format /0 /1 /2 /3
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MRM4r = 20, MRM5r = 21, MRM6r = 22, MRM7r = 23, // Format /4 /5 /6 /7
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// Next, instructions that operate on a memory r/m operand...
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MRM0m = 24, MRM1m = 25, MRM2m = 26, MRM3m = 27, // Format /0 /1 /2 /3
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MRM4m = 28, MRM5m = 29, MRM6m = 30, MRM7m = 31, // Format /4 /5 /6 /7
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// MRMInitReg - This form is used for instructions whose source and
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// destinations are the same register.
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MRMInitReg = 32,
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//// MRM_C1 - A mod/rm byte of exactly 0xC1.
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MRM_C1 = 33,
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MRM_C2 = 34,
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MRM_C3 = 35,
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MRM_C4 = 36,
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MRM_C8 = 37,
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MRM_C9 = 38,
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MRM_E8 = 39,
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MRM_F0 = 40,
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MRM_F8 = 41,
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MRM_F9 = 42,
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MRM_D0 = 45,
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MRM_D1 = 46,
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/// RawFrmImm8 - This is used for the ENTER instruction, which has two
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/// immediates, the first of which is a 16-bit immediate (specified by
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/// the imm encoding) and the second is a 8-bit fixed value.
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RawFrmImm8 = 43,
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/// RawFrmImm16 - This is used for CALL FAR instructions, which have two
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/// immediates, the first of which is a 16 or 32-bit immediate (specified by
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/// the imm encoding) and the second is a 16-bit fixed value. In the AMD
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/// manual, this operand is described as pntr16:32 and pntr16:16
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RawFrmImm16 = 44,
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FormMask = 63,
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//===------------------------------------------------------------------===//
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// Actual flags...
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// OpSize - Set if this instruction requires an operand size prefix (0x66),
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// which most often indicates that the instruction operates on 16 bit data
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// instead of 32 bit data.
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OpSize = 1 << 6,
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// AsSize - Set if this instruction requires an operand size prefix (0x67),
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// which most often indicates that the instruction address 16 bit address
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// instead of 32 bit address (or 32 bit address in 64 bit mode).
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AdSize = 1 << 7,
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//===------------------------------------------------------------------===//
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// Op0Mask - There are several prefix bytes that are used to form two byte
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// opcodes. These are currently 0x0F, 0xF3, and 0xD8-0xDF. This mask is
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// used to obtain the setting of this field. If no bits in this field is
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// set, there is no prefix byte for obtaining a multibyte opcode.
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//
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Op0Shift = 8,
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Op0Mask = 0x1F << Op0Shift,
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// TB - TwoByte - Set if this instruction has a two byte opcode, which
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// starts with a 0x0F byte before the real opcode.
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TB = 1 << Op0Shift,
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// REP - The 0xF3 prefix byte indicating repetition of the following
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// instruction.
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REP = 2 << Op0Shift,
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// D8-DF - These escape opcodes are used by the floating point unit. These
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// values must remain sequential.
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D8 = 3 << Op0Shift, D9 = 4 << Op0Shift,
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DA = 5 << Op0Shift, DB = 6 << Op0Shift,
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DC = 7 << Op0Shift, DD = 8 << Op0Shift,
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DE = 9 << Op0Shift, DF = 10 << Op0Shift,
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// XS, XD - These prefix codes are for single and double precision scalar
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// floating point operations performed in the SSE registers.
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XD = 11 << Op0Shift, XS = 12 << Op0Shift,
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// T8, TA, A6, A7 - Prefix after the 0x0F prefix.
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T8 = 13 << Op0Shift, TA = 14 << Op0Shift,
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A6 = 15 << Op0Shift, A7 = 16 << Op0Shift,
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// TF - Prefix before and after 0x0F
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TF = 17 << Op0Shift,
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//===------------------------------------------------------------------===//
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// REX_W - REX prefixes are instruction prefixes used in 64-bit mode.
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// They are used to specify GPRs and SSE registers, 64-bit operand size,
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// etc. We only cares about REX.W and REX.R bits and only the former is
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// statically determined.
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//
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REXShift = Op0Shift + 5,
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REX_W = 1 << REXShift,
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//===------------------------------------------------------------------===//
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// This three-bit field describes the size of an immediate operand. Zero is
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// unused so that we can tell if we forgot to set a value.
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ImmShift = REXShift + 1,
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ImmMask = 7 << ImmShift,
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Imm8 = 1 << ImmShift,
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Imm8PCRel = 2 << ImmShift,
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Imm16 = 3 << ImmShift,
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Imm16PCRel = 4 << ImmShift,
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Imm32 = 5 << ImmShift,
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Imm32PCRel = 6 << ImmShift,
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Imm64 = 7 << ImmShift,
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//===------------------------------------------------------------------===//
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// FP Instruction Classification... Zero is non-fp instruction.
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// FPTypeMask - Mask for all of the FP types...
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FPTypeShift = ImmShift + 3,
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FPTypeMask = 7 << FPTypeShift,
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// NotFP - The default, set for instructions that do not use FP registers.
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NotFP = 0 << FPTypeShift,
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// ZeroArgFP - 0 arg FP instruction which implicitly pushes ST(0), f.e. fld0
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ZeroArgFP = 1 << FPTypeShift,
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// OneArgFP - 1 arg FP instructions which implicitly read ST(0), such as fst
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OneArgFP = 2 << FPTypeShift,
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// OneArgFPRW - 1 arg FP instruction which implicitly read ST(0) and write a
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// result back to ST(0). For example, fcos, fsqrt, etc.
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//
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OneArgFPRW = 3 << FPTypeShift,
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// TwoArgFP - 2 arg FP instructions which implicitly read ST(0), and an
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// explicit argument, storing the result to either ST(0) or the implicit
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// argument. For example: fadd, fsub, fmul, etc...
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TwoArgFP = 4 << FPTypeShift,
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// CompareFP - 2 arg FP instructions which implicitly read ST(0) and an
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// explicit argument, but have no destination. Example: fucom, fucomi, ...
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CompareFP = 5 << FPTypeShift,
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// CondMovFP - "2 operand" floating point conditional move instructions.
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CondMovFP = 6 << FPTypeShift,
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// SpecialFP - Special instruction forms. Dispatch by opcode explicitly.
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SpecialFP = 7 << FPTypeShift,
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// Lock prefix
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LOCKShift = FPTypeShift + 3,
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LOCK = 1 << LOCKShift,
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// Segment override prefixes. Currently we just need ability to address
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// stuff in gs and fs segments.
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SegOvrShift = LOCKShift + 1,
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SegOvrMask = 3 << SegOvrShift,
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FS = 1 << SegOvrShift,
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GS = 2 << SegOvrShift,
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// Execution domain for SSE instructions in bits 23, 24.
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// 0 in bits 23-24 means normal, non-SSE instruction.
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SSEDomainShift = SegOvrShift + 2,
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OpcodeShift = SSEDomainShift + 2,
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//===------------------------------------------------------------------===//
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/// VEX - The opcode prefix used by AVX instructions
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VEXShift = OpcodeShift + 8,
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VEX = 1U << 0,
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/// VEX_W - Has a opcode specific functionality, but is used in the same
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/// way as REX_W is for regular SSE instructions.
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VEX_W = 1U << 1,
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/// VEX_4V - Used to specify an additional AVX/SSE register. Several 2
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/// address instructions in SSE are represented as 3 address ones in AVX
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/// and the additional register is encoded in VEX_VVVV prefix.
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VEX_4V = 1U << 2,
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/// VEX_I8IMM - Specifies that the last register used in a AVX instruction,
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/// must be encoded in the i8 immediate field. This usually happens in
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/// instructions with 4 operands.
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VEX_I8IMM = 1U << 3,
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/// VEX_L - Stands for a bit in the VEX opcode prefix meaning the current
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/// instruction uses 256-bit wide registers. This is usually auto detected
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/// if a VR256 register is used, but some AVX instructions also have this
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/// field marked when using a f256 memory references.
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VEX_L = 1U << 4,
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/// Has3DNow0F0FOpcode - This flag indicates that the instruction uses the
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/// wacky 0x0F 0x0F prefix for 3DNow! instructions. The manual documents
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/// this as having a 0x0F prefix with a 0x0F opcode, and each instruction
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/// storing a classifier in the imm8 field. To simplify our implementation,
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/// we handle this by storeing the classifier in the opcode field and using
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/// this flag to indicate that the encoder should do the wacky 3DNow! thing.
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Has3DNow0F0FOpcode = 1U << 5
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};
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// getBaseOpcodeFor - This function returns the "base" X86 opcode for the
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// specified machine instruction.
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//
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static inline unsigned char getBaseOpcodeFor(uint64_t TSFlags) {
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return TSFlags >> X86II::OpcodeShift;
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}
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static inline bool hasImm(uint64_t TSFlags) {
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return (TSFlags & X86II::ImmMask) != 0;
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}
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/// getSizeOfImm - Decode the "size of immediate" field from the TSFlags field
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/// of the specified instruction.
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static inline unsigned getSizeOfImm(uint64_t TSFlags) {
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switch (TSFlags & X86II::ImmMask) {
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default: assert(0 && "Unknown immediate size");
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case X86II::Imm8:
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case X86II::Imm8PCRel: return 1;
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case X86II::Imm16:
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case X86II::Imm16PCRel: return 2;
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case X86II::Imm32:
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case X86II::Imm32PCRel: return 4;
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case X86II::Imm64: return 8;
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}
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}
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/// isImmPCRel - Return true if the immediate of the specified instruction's
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/// TSFlags indicates that it is pc relative.
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static inline unsigned isImmPCRel(uint64_t TSFlags) {
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switch (TSFlags & X86II::ImmMask) {
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default: assert(0 && "Unknown immediate size");
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case X86II::Imm8PCRel:
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case X86II::Imm16PCRel:
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case X86II::Imm32PCRel:
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return true;
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case X86II::Imm8:
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case X86II::Imm16:
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case X86II::Imm32:
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case X86II::Imm64:
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return false;
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}
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}
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/// getMemoryOperandNo - The function returns the MCInst operand # for the
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/// first field of the memory operand. If the instruction doesn't have a
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/// memory operand, this returns -1.
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///
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/// Note that this ignores tied operands. If there is a tied register which
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/// is duplicated in the MCInst (e.g. "EAX = addl EAX, [mem]") it is only
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/// counted as one operand.
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///
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static inline int getMemoryOperandNo(uint64_t TSFlags) {
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switch (TSFlags & X86II::FormMask) {
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case X86II::MRMInitReg: assert(0 && "FIXME: Remove this form");
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default: assert(0 && "Unknown FormMask value in getMemoryOperandNo!");
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case X86II::Pseudo:
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case X86II::RawFrm:
|
|
case X86II::AddRegFrm:
|
|
case X86II::MRMDestReg:
|
|
case X86II::MRMSrcReg:
|
|
case X86II::RawFrmImm8:
|
|
case X86II::RawFrmImm16:
|
|
return -1;
|
|
case X86II::MRMDestMem:
|
|
return 0;
|
|
case X86II::MRMSrcMem: {
|
|
bool HasVEX_4V = (TSFlags >> X86II::VEXShift) & X86II::VEX_4V;
|
|
unsigned FirstMemOp = 1;
|
|
if (HasVEX_4V)
|
|
++FirstMemOp;// Skip the register source (which is encoded in VEX_VVVV).
|
|
|
|
// FIXME: Maybe lea should have its own form? This is a horrible hack.
|
|
//if (Opcode == X86::LEA64r || Opcode == X86::LEA64_32r ||
|
|
// Opcode == X86::LEA16r || Opcode == X86::LEA32r)
|
|
return FirstMemOp;
|
|
}
|
|
case X86II::MRM0r: case X86II::MRM1r:
|
|
case X86II::MRM2r: case X86II::MRM3r:
|
|
case X86II::MRM4r: case X86II::MRM5r:
|
|
case X86II::MRM6r: case X86II::MRM7r:
|
|
return -1;
|
|
case X86II::MRM0m: case X86II::MRM1m:
|
|
case X86II::MRM2m: case X86II::MRM3m:
|
|
case X86II::MRM4m: case X86II::MRM5m:
|
|
case X86II::MRM6m: case X86II::MRM7m:
|
|
return 0;
|
|
case X86II::MRM_C1:
|
|
case X86II::MRM_C2:
|
|
case X86II::MRM_C3:
|
|
case X86II::MRM_C4:
|
|
case X86II::MRM_C8:
|
|
case X86II::MRM_C9:
|
|
case X86II::MRM_E8:
|
|
case X86II::MRM_F0:
|
|
case X86II::MRM_F8:
|
|
case X86II::MRM_F9:
|
|
case X86II::MRM_D0:
|
|
case X86II::MRM_D1:
|
|
return -1;
|
|
}
|
|
}
|
|
|
|
/// isX86_64ExtendedReg - Is the MachineOperand a x86-64 extended (r8 or
|
|
/// higher) register? e.g. r8, xmm8, xmm13, etc.
|
|
static inline bool isX86_64ExtendedReg(unsigned RegNo) {
|
|
switch (RegNo) {
|
|
default: break;
|
|
case X86::R8: case X86::R9: case X86::R10: case X86::R11:
|
|
case X86::R12: case X86::R13: case X86::R14: case X86::R15:
|
|
case X86::R8D: case X86::R9D: case X86::R10D: case X86::R11D:
|
|
case X86::R12D: case X86::R13D: case X86::R14D: case X86::R15D:
|
|
case X86::R8W: case X86::R9W: case X86::R10W: case X86::R11W:
|
|
case X86::R12W: case X86::R13W: case X86::R14W: case X86::R15W:
|
|
case X86::R8B: case X86::R9B: case X86::R10B: case X86::R11B:
|
|
case X86::R12B: case X86::R13B: case X86::R14B: case X86::R15B:
|
|
case X86::XMM8: case X86::XMM9: case X86::XMM10: case X86::XMM11:
|
|
case X86::XMM12: case X86::XMM13: case X86::XMM14: case X86::XMM15:
|
|
case X86::YMM8: case X86::YMM9: case X86::YMM10: case X86::YMM11:
|
|
case X86::YMM12: case X86::YMM13: case X86::YMM14: case X86::YMM15:
|
|
case X86::CR8: case X86::CR9: case X86::CR10: case X86::CR11:
|
|
case X86::CR12: case X86::CR13: case X86::CR14: case X86::CR15:
|
|
return true;
|
|
}
|
|
return false;
|
|
}
|
|
|
|
static inline bool isX86_64NonExtLowByteReg(unsigned reg) {
|
|
return (reg == X86::SPL || reg == X86::BPL ||
|
|
reg == X86::SIL || reg == X86::DIL);
|
|
}
|
|
}
|
|
|
|
} // end namespace llvm;
|
|
|
|
#endif
|