mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-09-01 04:29:57 +00:00
81f04d59f6
room for it. This is in preparation for another patch which is adding NEON subformats to facilitate disassembly. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98967 91177308-0d34-0410-b5e6-96231b3b80d8
1655 lines
59 KiB
TableGen
1655 lines
59 KiB
TableGen
//===- ARMInstrFormats.td - ARM Instruction Formats --*- tablegen -*---------=//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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//
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// ARM Instruction Format Definitions.
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//
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// Format specifies the encoding used by the instruction. This is part of the
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// ad-hoc solution used to emit machine instruction encodings by our machine
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// code emitter.
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class Format<bits<6> val> {
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bits<6> Value = val;
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}
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def Pseudo : Format<0>;
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def MulFrm : Format<1>;
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def BrFrm : Format<2>;
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def BrMiscFrm : Format<3>;
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def DPFrm : Format<4>;
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def DPSoRegFrm : Format<5>;
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def LdFrm : Format<6>;
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def StFrm : Format<7>;
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def LdMiscFrm : Format<8>;
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def StMiscFrm : Format<9>;
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def LdStMulFrm : Format<10>;
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def LdStExFrm : Format<11>;
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def ArithMiscFrm : Format<12>;
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def ExtFrm : Format<13>;
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def VFPUnaryFrm : Format<14>;
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def VFPBinaryFrm : Format<15>;
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def VFPConv1Frm : Format<16>;
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def VFPConv2Frm : Format<17>;
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def VFPConv3Frm : Format<18>;
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def VFPConv4Frm : Format<19>;
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def VFPConv5Frm : Format<20>;
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def VFPLdStFrm : Format<21>;
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def VFPLdStMulFrm : Format<22>;
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def VFPMiscFrm : Format<23>;
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def ThumbFrm : Format<24>;
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def NEONFrm : Format<25>;
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def NEONGetLnFrm : Format<26>;
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def NEONSetLnFrm : Format<27>;
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def NEONDupFrm : Format<28>;
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def MiscFrm : Format<29>;
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def ThumbMiscFrm : Format<30>;
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// Misc flags.
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// the instruction has a Rn register operand.
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// UnaryDP - Indicates this is a unary data processing instruction, i.e.
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// it doesn't have a Rn operand.
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class UnaryDP { bit isUnaryDataProc = 1; }
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// Xform16Bit - Indicates this Thumb2 instruction may be transformed into
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// a 16-bit Thumb instruction if certain conditions are met.
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class Xform16Bit { bit canXformTo16Bit = 1; }
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//===----------------------------------------------------------------------===//
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// ARM Instruction flags. These need to match ARMBaseInstrInfo.h.
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//
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// Addressing mode.
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class AddrMode<bits<4> val> {
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bits<4> Value = val;
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}
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def AddrModeNone : AddrMode<0>;
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def AddrMode1 : AddrMode<1>;
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def AddrMode2 : AddrMode<2>;
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def AddrMode3 : AddrMode<3>;
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def AddrMode4 : AddrMode<4>;
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def AddrMode5 : AddrMode<5>;
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def AddrMode6 : AddrMode<6>;
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def AddrModeT1_1 : AddrMode<7>;
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def AddrModeT1_2 : AddrMode<8>;
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def AddrModeT1_4 : AddrMode<9>;
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def AddrModeT1_s : AddrMode<10>;
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def AddrModeT2_i12: AddrMode<11>;
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def AddrModeT2_i8 : AddrMode<12>;
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def AddrModeT2_so : AddrMode<13>;
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def AddrModeT2_pc : AddrMode<14>;
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def AddrModeT2_i8s4 : AddrMode<15>;
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// Instruction size.
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class SizeFlagVal<bits<3> val> {
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bits<3> Value = val;
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}
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def SizeInvalid : SizeFlagVal<0>; // Unset.
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def SizeSpecial : SizeFlagVal<1>; // Pseudo or special.
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def Size8Bytes : SizeFlagVal<2>;
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def Size4Bytes : SizeFlagVal<3>;
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def Size2Bytes : SizeFlagVal<4>;
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// Load / store index mode.
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class IndexMode<bits<2> val> {
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bits<2> Value = val;
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}
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def IndexModeNone : IndexMode<0>;
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def IndexModePre : IndexMode<1>;
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def IndexModePost : IndexMode<2>;
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def IndexModeUpd : IndexMode<3>;
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// Instruction execution domain.
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class Domain<bits<2> val> {
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bits<2> Value = val;
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}
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def GenericDomain : Domain<0>;
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def VFPDomain : Domain<1>; // Instructions in VFP domain only
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def NeonDomain : Domain<2>; // Instructions in Neon domain only
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def VFPNeonDomain : Domain<3>; // Instructions in both VFP & Neon domains
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//===----------------------------------------------------------------------===//
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// ARM special operands.
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//
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// ARM Predicate operand. Default to 14 = always (AL). Second part is CC
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// register whose default is 0 (no register).
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def pred : PredicateOperand<OtherVT, (ops i32imm, CCR),
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(ops (i32 14), (i32 zero_reg))> {
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let PrintMethod = "printPredicateOperand";
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}
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// Conditional code result for instructions whose 's' bit is set, e.g. subs.
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def cc_out : OptionalDefOperand<OtherVT, (ops CCR), (ops (i32 zero_reg))> {
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let PrintMethod = "printSBitModifierOperand";
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}
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// Same as cc_out except it defaults to setting CPSR.
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def s_cc_out : OptionalDefOperand<OtherVT, (ops CCR), (ops (i32 CPSR))> {
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let PrintMethod = "printSBitModifierOperand";
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}
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// ARM special operands for disassembly only.
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//
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def cps_opt : Operand<i32> {
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let PrintMethod = "printCPSOptionOperand";
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}
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def msr_mask : Operand<i32> {
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let PrintMethod = "printMSRMaskOperand";
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}
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// A8.6.117, A8.6.118. Different instructions are generated for #0 and #-0.
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// The neg_zero operand translates -0 to -1, -1 to -2, ..., etc.
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def neg_zero : Operand<i32> {
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let PrintMethod = "printNegZeroOperand";
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}
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//===----------------------------------------------------------------------===//
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// ARM Instruction templates.
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//
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class InstTemplate<AddrMode am, SizeFlagVal sz, IndexMode im,
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Format f, Domain d, string cstr, InstrItinClass itin>
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: Instruction {
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let Namespace = "ARM";
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// TSFlagsFields
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AddrMode AM = am;
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bits<4> AddrModeBits = AM.Value;
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SizeFlagVal SZ = sz;
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bits<3> SizeFlag = SZ.Value;
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IndexMode IM = im;
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bits<2> IndexModeBits = IM.Value;
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Format F = f;
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bits<6> Form = F.Value;
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Domain D = d;
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bits<2> Dom = D.Value;
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//
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// Attributes specific to ARM instructions...
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//
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bit isUnaryDataProc = 0;
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bit canXformTo16Bit = 0;
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let Constraints = cstr;
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let Itinerary = itin;
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}
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class Encoding {
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field bits<32> Inst;
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}
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class InstARM<AddrMode am, SizeFlagVal sz, IndexMode im,
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Format f, Domain d, string cstr, InstrItinClass itin>
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: InstTemplate<am, sz, im, f, d, cstr, itin>, Encoding;
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// This Encoding-less class is used by Thumb1 to specify the encoding bits later
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// on by adding flavors to specific instructions.
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class InstThumb<AddrMode am, SizeFlagVal sz, IndexMode im,
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Format f, Domain d, string cstr, InstrItinClass itin>
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: InstTemplate<am, sz, im, f, d, cstr, itin>;
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class PseudoInst<dag oops, dag iops, InstrItinClass itin,
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string asm, list<dag> pattern>
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: InstARM<AddrModeNone, SizeSpecial, IndexModeNone, Pseudo, GenericDomain,
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"", itin> {
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let OutOperandList = oops;
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let InOperandList = iops;
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let AsmString = asm;
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let Pattern = pattern;
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}
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// Almost all ARM instructions are predicable.
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class I<dag oops, dag iops, AddrMode am, SizeFlagVal sz,
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IndexMode im, Format f, InstrItinClass itin,
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string opc, string asm, string cstr,
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list<dag> pattern>
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: InstARM<am, sz, im, f, GenericDomain, cstr, itin> {
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let OutOperandList = oops;
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let InOperandList = !con(iops, (ins pred:$p));
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let AsmString = !strconcat(opc, !strconcat("${p}", asm));
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let Pattern = pattern;
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list<Predicate> Predicates = [IsARM];
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}
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// A few are not predicable
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class InoP<dag oops, dag iops, AddrMode am, SizeFlagVal sz,
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IndexMode im, Format f, InstrItinClass itin,
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string opc, string asm, string cstr,
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list<dag> pattern>
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: InstARM<am, sz, im, f, GenericDomain, cstr, itin> {
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let OutOperandList = oops;
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let InOperandList = iops;
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let AsmString = !strconcat(opc, asm);
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let Pattern = pattern;
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let isPredicable = 0;
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list<Predicate> Predicates = [IsARM];
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}
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// Same as I except it can optionally modify CPSR. Note it's modeled as
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// an input operand since by default it's a zero register. It will
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// become an implicit def once it's "flipped".
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class sI<dag oops, dag iops, AddrMode am, SizeFlagVal sz,
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IndexMode im, Format f, InstrItinClass itin,
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string opc, string asm, string cstr,
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list<dag> pattern>
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: InstARM<am, sz, im, f, GenericDomain, cstr, itin> {
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let OutOperandList = oops;
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let InOperandList = !con(iops, (ins pred:$p, cc_out:$s));
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let AsmString = !strconcat(opc, !strconcat("${p}${s}", asm));
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let Pattern = pattern;
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list<Predicate> Predicates = [IsARM];
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}
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// Special cases
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class XI<dag oops, dag iops, AddrMode am, SizeFlagVal sz,
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IndexMode im, Format f, InstrItinClass itin,
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string asm, string cstr, list<dag> pattern>
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: InstARM<am, sz, im, f, GenericDomain, cstr, itin> {
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let OutOperandList = oops;
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let InOperandList = iops;
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let AsmString = asm;
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let Pattern = pattern;
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list<Predicate> Predicates = [IsARM];
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}
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class AI<dag oops, dag iops, Format f, InstrItinClass itin,
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string opc, string asm, list<dag> pattern>
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: I<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, f, itin,
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opc, asm, "", pattern>;
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class AsI<dag oops, dag iops, Format f, InstrItinClass itin,
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string opc, string asm, list<dag> pattern>
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: sI<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, f, itin,
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opc, asm, "", pattern>;
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class AXI<dag oops, dag iops, Format f, InstrItinClass itin,
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string asm, list<dag> pattern>
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: XI<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, f, itin,
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asm, "", pattern>;
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class AInoP<dag oops, dag iops, Format f, InstrItinClass itin,
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string opc, string asm, list<dag> pattern>
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: InoP<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, f, itin,
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opc, asm, "", pattern>;
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// Ctrl flow instructions
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class ABI<bits<4> opcod, dag oops, dag iops, InstrItinClass itin,
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string opc, string asm, list<dag> pattern>
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: I<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, BrFrm, itin,
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opc, asm, "", pattern> {
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let Inst{27-24} = opcod;
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}
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class ABXI<bits<4> opcod, dag oops, dag iops, InstrItinClass itin,
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string asm, list<dag> pattern>
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: XI<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, BrFrm, itin,
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asm, "", pattern> {
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let Inst{27-24} = opcod;
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}
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class ABXIx2<dag oops, dag iops, InstrItinClass itin,
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string asm, list<dag> pattern>
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: XI<oops, iops, AddrModeNone, Size8Bytes, IndexModeNone, BrMiscFrm, itin,
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asm, "", pattern>;
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// BR_JT instructions
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class JTI<dag oops, dag iops, InstrItinClass itin,
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string asm, list<dag> pattern>
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: XI<oops, iops, AddrModeNone, SizeSpecial, IndexModeNone, BrMiscFrm, itin,
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asm, "", pattern>;
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// Atomic load/store instructions
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class AIldrex<bits<2> opcod, dag oops, dag iops, InstrItinClass itin,
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string opc, string asm, list<dag> pattern>
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: I<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, LdStExFrm, itin,
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opc, asm, "", pattern> {
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let Inst{27-23} = 0b00011;
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let Inst{22-21} = opcod;
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let Inst{20} = 1;
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let Inst{11-0} = 0b111110011111;
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}
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class AIstrex<bits<2> opcod, dag oops, dag iops, InstrItinClass itin,
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string opc, string asm, list<dag> pattern>
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: I<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, LdStExFrm, itin,
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opc, asm, "", pattern> {
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let Inst{27-23} = 0b00011;
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let Inst{22-21} = opcod;
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let Inst{20} = 0;
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let Inst{11-4} = 0b11111001;
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}
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// addrmode1 instructions
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class AI1<bits<4> opcod, dag oops, dag iops, Format f, InstrItinClass itin,
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string opc, string asm, list<dag> pattern>
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: I<oops, iops, AddrMode1, Size4Bytes, IndexModeNone, f, itin,
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opc, asm, "", pattern> {
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let Inst{24-21} = opcod;
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let Inst{27-26} = {0,0};
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}
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class AsI1<bits<4> opcod, dag oops, dag iops, Format f, InstrItinClass itin,
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string opc, string asm, list<dag> pattern>
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: sI<oops, iops, AddrMode1, Size4Bytes, IndexModeNone, f, itin,
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opc, asm, "", pattern> {
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let Inst{24-21} = opcod;
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let Inst{27-26} = {0,0};
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}
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class AXI1<bits<4> opcod, dag oops, dag iops, Format f, InstrItinClass itin,
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string asm, list<dag> pattern>
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: XI<oops, iops, AddrMode1, Size4Bytes, IndexModeNone, f, itin,
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asm, "", pattern> {
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let Inst{24-21} = opcod;
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let Inst{27-26} = {0,0};
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}
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class AI1x2<dag oops, dag iops, Format f, InstrItinClass itin,
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string opc, string asm, list<dag> pattern>
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: I<oops, iops, AddrMode1, Size8Bytes, IndexModeNone, f, itin,
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opc, asm, "", pattern>;
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// addrmode2 loads and stores
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class AI2<dag oops, dag iops, Format f, InstrItinClass itin,
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string opc, string asm, list<dag> pattern>
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: I<oops, iops, AddrMode2, Size4Bytes, IndexModeNone, f, itin,
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opc, asm, "", pattern> {
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let Inst{27-26} = {0,1};
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}
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// loads
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class AI2ldw<dag oops, dag iops, Format f, InstrItinClass itin,
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string opc, string asm, list<dag> pattern>
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: I<oops, iops, AddrMode2, Size4Bytes, IndexModeNone, f, itin,
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opc, asm, "", pattern> {
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let Inst{20} = 1; // L bit
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let Inst{21} = 0; // W bit
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let Inst{22} = 0; // B bit
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let Inst{24} = 1; // P bit
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let Inst{27-26} = {0,1};
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}
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class AXI2ldw<dag oops, dag iops, Format f, InstrItinClass itin,
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string asm, list<dag> pattern>
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: XI<oops, iops, AddrMode2, Size4Bytes, IndexModeNone, f, itin,
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asm, "", pattern> {
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let Inst{20} = 1; // L bit
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let Inst{21} = 0; // W bit
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let Inst{22} = 0; // B bit
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let Inst{24} = 1; // P bit
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let Inst{27-26} = {0,1};
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}
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class AI2ldb<dag oops, dag iops, Format f, InstrItinClass itin,
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string opc, string asm, list<dag> pattern>
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: I<oops, iops, AddrMode2, Size4Bytes, IndexModeNone, f, itin,
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opc, asm, "", pattern> {
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let Inst{20} = 1; // L bit
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let Inst{21} = 0; // W bit
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let Inst{22} = 1; // B bit
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let Inst{24} = 1; // P bit
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let Inst{27-26} = {0,1};
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}
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class AXI2ldb<dag oops, dag iops, Format f, InstrItinClass itin,
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string asm, list<dag> pattern>
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: XI<oops, iops, AddrMode2, Size4Bytes, IndexModeNone, f, itin,
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asm, "", pattern> {
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let Inst{20} = 1; // L bit
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let Inst{21} = 0; // W bit
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let Inst{22} = 1; // B bit
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let Inst{24} = 1; // P bit
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let Inst{27-26} = {0,1};
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}
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// stores
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class AI2stw<dag oops, dag iops, Format f, InstrItinClass itin,
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string opc, string asm, list<dag> pattern>
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: I<oops, iops, AddrMode2, Size4Bytes, IndexModeNone, f, itin,
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opc, asm, "", pattern> {
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let Inst{20} = 0; // L bit
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let Inst{21} = 0; // W bit
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let Inst{22} = 0; // B bit
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let Inst{24} = 1; // P bit
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let Inst{27-26} = {0,1};
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}
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class AXI2stw<dag oops, dag iops, Format f, InstrItinClass itin,
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string asm, list<dag> pattern>
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: XI<oops, iops, AddrMode2, Size4Bytes, IndexModeNone, f, itin,
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asm, "", pattern> {
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let Inst{20} = 0; // L bit
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let Inst{21} = 0; // W bit
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let Inst{22} = 0; // B bit
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let Inst{24} = 1; // P bit
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let Inst{27-26} = {0,1};
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}
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class AI2stb<dag oops, dag iops, Format f, InstrItinClass itin,
|
|
string opc, string asm, list<dag> pattern>
|
|
: I<oops, iops, AddrMode2, Size4Bytes, IndexModeNone, f, itin,
|
|
opc, asm, "", pattern> {
|
|
let Inst{20} = 0; // L bit
|
|
let Inst{21} = 0; // W bit
|
|
let Inst{22} = 1; // B bit
|
|
let Inst{24} = 1; // P bit
|
|
let Inst{27-26} = {0,1};
|
|
}
|
|
class AXI2stb<dag oops, dag iops, Format f, InstrItinClass itin,
|
|
string asm, list<dag> pattern>
|
|
: XI<oops, iops, AddrMode2, Size4Bytes, IndexModeNone, f, itin,
|
|
asm, "", pattern> {
|
|
let Inst{20} = 0; // L bit
|
|
let Inst{21} = 0; // W bit
|
|
let Inst{22} = 1; // B bit
|
|
let Inst{24} = 1; // P bit
|
|
let Inst{27-26} = {0,1};
|
|
}
|
|
|
|
// Pre-indexed loads
|
|
class AI2ldwpr<dag oops, dag iops, Format f, InstrItinClass itin,
|
|
string opc, string asm, string cstr, list<dag> pattern>
|
|
: I<oops, iops, AddrMode2, Size4Bytes, IndexModePre, f, itin,
|
|
opc, asm, cstr, pattern> {
|
|
let Inst{20} = 1; // L bit
|
|
let Inst{21} = 1; // W bit
|
|
let Inst{22} = 0; // B bit
|
|
let Inst{24} = 1; // P bit
|
|
let Inst{27-26} = {0,1};
|
|
}
|
|
class AI2ldbpr<dag oops, dag iops, Format f, InstrItinClass itin,
|
|
string opc, string asm, string cstr, list<dag> pattern>
|
|
: I<oops, iops, AddrMode2, Size4Bytes, IndexModePre, f, itin,
|
|
opc, asm, cstr, pattern> {
|
|
let Inst{20} = 1; // L bit
|
|
let Inst{21} = 1; // W bit
|
|
let Inst{22} = 1; // B bit
|
|
let Inst{24} = 1; // P bit
|
|
let Inst{27-26} = {0,1};
|
|
}
|
|
|
|
// Pre-indexed stores
|
|
class AI2stwpr<dag oops, dag iops, Format f, InstrItinClass itin,
|
|
string opc, string asm, string cstr, list<dag> pattern>
|
|
: I<oops, iops, AddrMode2, Size4Bytes, IndexModePre, f, itin,
|
|
opc, asm, cstr, pattern> {
|
|
let Inst{20} = 0; // L bit
|
|
let Inst{21} = 1; // W bit
|
|
let Inst{22} = 0; // B bit
|
|
let Inst{24} = 1; // P bit
|
|
let Inst{27-26} = {0,1};
|
|
}
|
|
class AI2stbpr<dag oops, dag iops, Format f, InstrItinClass itin,
|
|
string opc, string asm, string cstr, list<dag> pattern>
|
|
: I<oops, iops, AddrMode2, Size4Bytes, IndexModePre, f, itin,
|
|
opc, asm, cstr, pattern> {
|
|
let Inst{20} = 0; // L bit
|
|
let Inst{21} = 1; // W bit
|
|
let Inst{22} = 1; // B bit
|
|
let Inst{24} = 1; // P bit
|
|
let Inst{27-26} = {0,1};
|
|
}
|
|
|
|
// Post-indexed loads
|
|
class AI2ldwpo<dag oops, dag iops, Format f, InstrItinClass itin,
|
|
string opc, string asm, string cstr, list<dag> pattern>
|
|
: I<oops, iops, AddrMode2, Size4Bytes, IndexModePost, f, itin,
|
|
opc, asm, cstr,pattern> {
|
|
let Inst{20} = 1; // L bit
|
|
let Inst{21} = 0; // W bit
|
|
let Inst{22} = 0; // B bit
|
|
let Inst{24} = 0; // P bit
|
|
let Inst{27-26} = {0,1};
|
|
}
|
|
class AI2ldbpo<dag oops, dag iops, Format f, InstrItinClass itin,
|
|
string opc, string asm, string cstr, list<dag> pattern>
|
|
: I<oops, iops, AddrMode2, Size4Bytes, IndexModePost, f, itin,
|
|
opc, asm, cstr,pattern> {
|
|
let Inst{20} = 1; // L bit
|
|
let Inst{21} = 0; // W bit
|
|
let Inst{22} = 1; // B bit
|
|
let Inst{24} = 0; // P bit
|
|
let Inst{27-26} = {0,1};
|
|
}
|
|
|
|
// Post-indexed stores
|
|
class AI2stwpo<dag oops, dag iops, Format f, InstrItinClass itin,
|
|
string opc, string asm, string cstr, list<dag> pattern>
|
|
: I<oops, iops, AddrMode2, Size4Bytes, IndexModePost, f, itin,
|
|
opc, asm, cstr,pattern> {
|
|
let Inst{20} = 0; // L bit
|
|
let Inst{21} = 0; // W bit
|
|
let Inst{22} = 0; // B bit
|
|
let Inst{24} = 0; // P bit
|
|
let Inst{27-26} = {0,1};
|
|
}
|
|
class AI2stbpo<dag oops, dag iops, Format f, InstrItinClass itin,
|
|
string opc, string asm, string cstr, list<dag> pattern>
|
|
: I<oops, iops, AddrMode2, Size4Bytes, IndexModePost, f, itin,
|
|
opc, asm, cstr,pattern> {
|
|
let Inst{20} = 0; // L bit
|
|
let Inst{21} = 0; // W bit
|
|
let Inst{22} = 1; // B bit
|
|
let Inst{24} = 0; // P bit
|
|
let Inst{27-26} = {0,1};
|
|
}
|
|
|
|
// addrmode3 instructions
|
|
class AI3<dag oops, dag iops, Format f, InstrItinClass itin,
|
|
string opc, string asm, list<dag> pattern>
|
|
: I<oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, itin,
|
|
opc, asm, "", pattern>;
|
|
class AXI3<dag oops, dag iops, Format f, InstrItinClass itin,
|
|
string asm, list<dag> pattern>
|
|
: XI<oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, itin,
|
|
asm, "", pattern>;
|
|
|
|
// loads
|
|
class AI3ldh<dag oops, dag iops, Format f, InstrItinClass itin,
|
|
string opc, string asm, list<dag> pattern>
|
|
: I<oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, itin,
|
|
opc, asm, "", pattern> {
|
|
let Inst{4} = 1;
|
|
let Inst{5} = 1; // H bit
|
|
let Inst{6} = 0; // S bit
|
|
let Inst{7} = 1;
|
|
let Inst{20} = 1; // L bit
|
|
let Inst{21} = 0; // W bit
|
|
let Inst{24} = 1; // P bit
|
|
let Inst{27-25} = 0b000;
|
|
}
|
|
class AXI3ldh<dag oops, dag iops, Format f, InstrItinClass itin,
|
|
string asm, list<dag> pattern>
|
|
: XI<oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, itin,
|
|
asm, "", pattern> {
|
|
let Inst{4} = 1;
|
|
let Inst{5} = 1; // H bit
|
|
let Inst{6} = 0; // S bit
|
|
let Inst{7} = 1;
|
|
let Inst{20} = 1; // L bit
|
|
let Inst{21} = 0; // W bit
|
|
let Inst{24} = 1; // P bit
|
|
}
|
|
class AI3ldsh<dag oops, dag iops, Format f, InstrItinClass itin,
|
|
string opc, string asm, list<dag> pattern>
|
|
: I<oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, itin,
|
|
opc, asm, "", pattern> {
|
|
let Inst{4} = 1;
|
|
let Inst{5} = 1; // H bit
|
|
let Inst{6} = 1; // S bit
|
|
let Inst{7} = 1;
|
|
let Inst{20} = 1; // L bit
|
|
let Inst{21} = 0; // W bit
|
|
let Inst{24} = 1; // P bit
|
|
let Inst{27-25} = 0b000;
|
|
}
|
|
class AXI3ldsh<dag oops, dag iops, Format f, InstrItinClass itin,
|
|
string asm, list<dag> pattern>
|
|
: XI<oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, itin,
|
|
asm, "", pattern> {
|
|
let Inst{4} = 1;
|
|
let Inst{5} = 1; // H bit
|
|
let Inst{6} = 1; // S bit
|
|
let Inst{7} = 1;
|
|
let Inst{20} = 1; // L bit
|
|
let Inst{21} = 0; // W bit
|
|
let Inst{24} = 1; // P bit
|
|
}
|
|
class AI3ldsb<dag oops, dag iops, Format f, InstrItinClass itin,
|
|
string opc, string asm, list<dag> pattern>
|
|
: I<oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, itin,
|
|
opc, asm, "", pattern> {
|
|
let Inst{4} = 1;
|
|
let Inst{5} = 0; // H bit
|
|
let Inst{6} = 1; // S bit
|
|
let Inst{7} = 1;
|
|
let Inst{20} = 1; // L bit
|
|
let Inst{21} = 0; // W bit
|
|
let Inst{24} = 1; // P bit
|
|
let Inst{27-25} = 0b000;
|
|
}
|
|
class AXI3ldsb<dag oops, dag iops, Format f, InstrItinClass itin,
|
|
string asm, list<dag> pattern>
|
|
: XI<oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, itin,
|
|
asm, "", pattern> {
|
|
let Inst{4} = 1;
|
|
let Inst{5} = 0; // H bit
|
|
let Inst{6} = 1; // S bit
|
|
let Inst{7} = 1;
|
|
let Inst{20} = 1; // L bit
|
|
let Inst{21} = 0; // W bit
|
|
let Inst{24} = 1; // P bit
|
|
}
|
|
class AI3ldd<dag oops, dag iops, Format f, InstrItinClass itin,
|
|
string opc, string asm, list<dag> pattern>
|
|
: I<oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, itin,
|
|
opc, asm, "", pattern> {
|
|
let Inst{4} = 1;
|
|
let Inst{5} = 0; // H bit
|
|
let Inst{6} = 1; // S bit
|
|
let Inst{7} = 1;
|
|
let Inst{20} = 0; // L bit
|
|
let Inst{21} = 0; // W bit
|
|
let Inst{24} = 1; // P bit
|
|
let Inst{27-25} = 0b000;
|
|
}
|
|
|
|
// stores
|
|
class AI3sth<dag oops, dag iops, Format f, InstrItinClass itin,
|
|
string opc, string asm, list<dag> pattern>
|
|
: I<oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, itin,
|
|
opc, asm, "", pattern> {
|
|
let Inst{4} = 1;
|
|
let Inst{5} = 1; // H bit
|
|
let Inst{6} = 0; // S bit
|
|
let Inst{7} = 1;
|
|
let Inst{20} = 0; // L bit
|
|
let Inst{21} = 0; // W bit
|
|
let Inst{24} = 1; // P bit
|
|
let Inst{27-25} = 0b000;
|
|
}
|
|
class AXI3sth<dag oops, dag iops, Format f, InstrItinClass itin,
|
|
string asm, list<dag> pattern>
|
|
: XI<oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, itin,
|
|
asm, "", pattern> {
|
|
let Inst{4} = 1;
|
|
let Inst{5} = 1; // H bit
|
|
let Inst{6} = 0; // S bit
|
|
let Inst{7} = 1;
|
|
let Inst{20} = 0; // L bit
|
|
let Inst{21} = 0; // W bit
|
|
let Inst{24} = 1; // P bit
|
|
}
|
|
class AI3std<dag oops, dag iops, Format f, InstrItinClass itin,
|
|
string opc, string asm, list<dag> pattern>
|
|
: I<oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, itin,
|
|
opc, asm, "", pattern> {
|
|
let Inst{4} = 1;
|
|
let Inst{5} = 1; // H bit
|
|
let Inst{6} = 1; // S bit
|
|
let Inst{7} = 1;
|
|
let Inst{20} = 0; // L bit
|
|
let Inst{21} = 0; // W bit
|
|
let Inst{24} = 1; // P bit
|
|
let Inst{27-25} = 0b000;
|
|
}
|
|
|
|
// Pre-indexed loads
|
|
class AI3ldhpr<dag oops, dag iops, Format f, InstrItinClass itin,
|
|
string opc, string asm, string cstr, list<dag> pattern>
|
|
: I<oops, iops, AddrMode3, Size4Bytes, IndexModePre, f, itin,
|
|
opc, asm, cstr, pattern> {
|
|
let Inst{4} = 1;
|
|
let Inst{5} = 1; // H bit
|
|
let Inst{6} = 0; // S bit
|
|
let Inst{7} = 1;
|
|
let Inst{20} = 1; // L bit
|
|
let Inst{21} = 1; // W bit
|
|
let Inst{24} = 1; // P bit
|
|
let Inst{27-25} = 0b000;
|
|
}
|
|
class AI3ldshpr<dag oops, dag iops, Format f, InstrItinClass itin,
|
|
string opc, string asm, string cstr, list<dag> pattern>
|
|
: I<oops, iops, AddrMode3, Size4Bytes, IndexModePre, f, itin,
|
|
opc, asm, cstr, pattern> {
|
|
let Inst{4} = 1;
|
|
let Inst{5} = 1; // H bit
|
|
let Inst{6} = 1; // S bit
|
|
let Inst{7} = 1;
|
|
let Inst{20} = 1; // L bit
|
|
let Inst{21} = 1; // W bit
|
|
let Inst{24} = 1; // P bit
|
|
let Inst{27-25} = 0b000;
|
|
}
|
|
class AI3ldsbpr<dag oops, dag iops, Format f, InstrItinClass itin,
|
|
string opc, string asm, string cstr, list<dag> pattern>
|
|
: I<oops, iops, AddrMode3, Size4Bytes, IndexModePre, f, itin,
|
|
opc, asm, cstr, pattern> {
|
|
let Inst{4} = 1;
|
|
let Inst{5} = 0; // H bit
|
|
let Inst{6} = 1; // S bit
|
|
let Inst{7} = 1;
|
|
let Inst{20} = 1; // L bit
|
|
let Inst{21} = 1; // W bit
|
|
let Inst{24} = 1; // P bit
|
|
let Inst{27-25} = 0b000;
|
|
}
|
|
class AI3lddpr<dag oops, dag iops, Format f, InstrItinClass itin,
|
|
string opc, string asm, string cstr, list<dag> pattern>
|
|
: I<oops, iops, AddrMode3, Size4Bytes, IndexModePre, f, itin,
|
|
opc, asm, cstr, pattern> {
|
|
let Inst{4} = 1;
|
|
let Inst{5} = 0; // H bit
|
|
let Inst{6} = 1; // S bit
|
|
let Inst{7} = 1;
|
|
let Inst{20} = 0; // L bit
|
|
let Inst{21} = 1; // W bit
|
|
let Inst{24} = 1; // P bit
|
|
let Inst{27-25} = 0b000;
|
|
}
|
|
|
|
|
|
// Pre-indexed stores
|
|
class AI3sthpr<dag oops, dag iops, Format f, InstrItinClass itin,
|
|
string opc, string asm, string cstr, list<dag> pattern>
|
|
: I<oops, iops, AddrMode3, Size4Bytes, IndexModePre, f, itin,
|
|
opc, asm, cstr, pattern> {
|
|
let Inst{4} = 1;
|
|
let Inst{5} = 1; // H bit
|
|
let Inst{6} = 0; // S bit
|
|
let Inst{7} = 1;
|
|
let Inst{20} = 0; // L bit
|
|
let Inst{21} = 1; // W bit
|
|
let Inst{24} = 1; // P bit
|
|
let Inst{27-25} = 0b000;
|
|
}
|
|
class AI3stdpr<dag oops, dag iops, Format f, InstrItinClass itin,
|
|
string opc, string asm, string cstr, list<dag> pattern>
|
|
: I<oops, iops, AddrMode3, Size4Bytes, IndexModePre, f, itin,
|
|
opc, asm, cstr, pattern> {
|
|
let Inst{4} = 1;
|
|
let Inst{5} = 1; // H bit
|
|
let Inst{6} = 1; // S bit
|
|
let Inst{7} = 1;
|
|
let Inst{20} = 0; // L bit
|
|
let Inst{21} = 1; // W bit
|
|
let Inst{24} = 1; // P bit
|
|
let Inst{27-25} = 0b000;
|
|
}
|
|
|
|
// Post-indexed loads
|
|
class AI3ldhpo<dag oops, dag iops, Format f, InstrItinClass itin,
|
|
string opc, string asm, string cstr, list<dag> pattern>
|
|
: I<oops, iops, AddrMode3, Size4Bytes, IndexModePost, f, itin,
|
|
opc, asm, cstr,pattern> {
|
|
let Inst{4} = 1;
|
|
let Inst{5} = 1; // H bit
|
|
let Inst{6} = 0; // S bit
|
|
let Inst{7} = 1;
|
|
let Inst{20} = 1; // L bit
|
|
let Inst{21} = 0; // W bit
|
|
let Inst{24} = 0; // P bit
|
|
let Inst{27-25} = 0b000;
|
|
}
|
|
class AI3ldshpo<dag oops, dag iops, Format f, InstrItinClass itin,
|
|
string opc, string asm, string cstr, list<dag> pattern>
|
|
: I<oops, iops, AddrMode3, Size4Bytes, IndexModePost, f, itin,
|
|
opc, asm, cstr,pattern> {
|
|
let Inst{4} = 1;
|
|
let Inst{5} = 1; // H bit
|
|
let Inst{6} = 1; // S bit
|
|
let Inst{7} = 1;
|
|
let Inst{20} = 1; // L bit
|
|
let Inst{21} = 0; // W bit
|
|
let Inst{24} = 0; // P bit
|
|
let Inst{27-25} = 0b000;
|
|
}
|
|
class AI3ldsbpo<dag oops, dag iops, Format f, InstrItinClass itin,
|
|
string opc, string asm, string cstr, list<dag> pattern>
|
|
: I<oops, iops, AddrMode3, Size4Bytes, IndexModePost, f, itin,
|
|
opc, asm, cstr,pattern> {
|
|
let Inst{4} = 1;
|
|
let Inst{5} = 0; // H bit
|
|
let Inst{6} = 1; // S bit
|
|
let Inst{7} = 1;
|
|
let Inst{20} = 1; // L bit
|
|
let Inst{21} = 0; // W bit
|
|
let Inst{24} = 0; // P bit
|
|
let Inst{27-25} = 0b000;
|
|
}
|
|
class AI3lddpo<dag oops, dag iops, Format f, InstrItinClass itin,
|
|
string opc, string asm, string cstr, list<dag> pattern>
|
|
: I<oops, iops, AddrMode3, Size4Bytes, IndexModePost, f, itin,
|
|
opc, asm, cstr, pattern> {
|
|
let Inst{4} = 1;
|
|
let Inst{5} = 0; // H bit
|
|
let Inst{6} = 1; // S bit
|
|
let Inst{7} = 1;
|
|
let Inst{20} = 0; // L bit
|
|
let Inst{21} = 0; // W bit
|
|
let Inst{24} = 0; // P bit
|
|
let Inst{27-25} = 0b000;
|
|
}
|
|
|
|
// Post-indexed stores
|
|
class AI3sthpo<dag oops, dag iops, Format f, InstrItinClass itin,
|
|
string opc, string asm, string cstr, list<dag> pattern>
|
|
: I<oops, iops, AddrMode3, Size4Bytes, IndexModePost, f, itin,
|
|
opc, asm, cstr,pattern> {
|
|
let Inst{4} = 1;
|
|
let Inst{5} = 1; // H bit
|
|
let Inst{6} = 0; // S bit
|
|
let Inst{7} = 1;
|
|
let Inst{20} = 0; // L bit
|
|
let Inst{21} = 0; // W bit
|
|
let Inst{24} = 0; // P bit
|
|
let Inst{27-25} = 0b000;
|
|
}
|
|
class AI3stdpo<dag oops, dag iops, Format f, InstrItinClass itin,
|
|
string opc, string asm, string cstr, list<dag> pattern>
|
|
: I<oops, iops, AddrMode3, Size4Bytes, IndexModePost, f, itin,
|
|
opc, asm, cstr, pattern> {
|
|
let Inst{4} = 1;
|
|
let Inst{5} = 1; // H bit
|
|
let Inst{6} = 1; // S bit
|
|
let Inst{7} = 1;
|
|
let Inst{20} = 0; // L bit
|
|
let Inst{21} = 0; // W bit
|
|
let Inst{24} = 0; // P bit
|
|
let Inst{27-25} = 0b000;
|
|
}
|
|
|
|
|
|
// addrmode4 instructions
|
|
class AXI4ld<dag oops, dag iops, IndexMode im, Format f, InstrItinClass itin,
|
|
string asm, string cstr, list<dag> pattern>
|
|
: XI<oops, iops, AddrMode4, Size4Bytes, im, f, itin,
|
|
asm, cstr, pattern> {
|
|
let Inst{20} = 1; // L bit
|
|
let Inst{22} = 0; // S bit
|
|
let Inst{27-25} = 0b100;
|
|
}
|
|
class AXI4st<dag oops, dag iops, IndexMode im, Format f, InstrItinClass itin,
|
|
string asm, string cstr, list<dag> pattern>
|
|
: XI<oops, iops, AddrMode4, Size4Bytes, im, f, itin,
|
|
asm, cstr, pattern> {
|
|
let Inst{20} = 0; // L bit
|
|
let Inst{22} = 0; // S bit
|
|
let Inst{27-25} = 0b100;
|
|
}
|
|
|
|
// Unsigned multiply, multiply-accumulate instructions.
|
|
class AMul1I<bits<7> opcod, dag oops, dag iops, InstrItinClass itin,
|
|
string opc, string asm, list<dag> pattern>
|
|
: I<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, MulFrm, itin,
|
|
opc, asm, "", pattern> {
|
|
let Inst{7-4} = 0b1001;
|
|
let Inst{20} = 0; // S bit
|
|
let Inst{27-21} = opcod;
|
|
}
|
|
class AsMul1I<bits<7> opcod, dag oops, dag iops, InstrItinClass itin,
|
|
string opc, string asm, list<dag> pattern>
|
|
: sI<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, MulFrm, itin,
|
|
opc, asm, "", pattern> {
|
|
let Inst{7-4} = 0b1001;
|
|
let Inst{27-21} = opcod;
|
|
}
|
|
|
|
// Most significant word multiply
|
|
class AMul2I<bits<7> opcod, dag oops, dag iops, InstrItinClass itin,
|
|
string opc, string asm, list<dag> pattern>
|
|
: I<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, MulFrm, itin,
|
|
opc, asm, "", pattern> {
|
|
let Inst{7-4} = 0b1001;
|
|
let Inst{20} = 1;
|
|
let Inst{27-21} = opcod;
|
|
}
|
|
|
|
// SMUL<x><y> / SMULW<y> / SMLA<x><y> / SMLAW<x><y>
|
|
class AMulxyI<bits<7> opcod, dag oops, dag iops, InstrItinClass itin,
|
|
string opc, string asm, list<dag> pattern>
|
|
: I<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, MulFrm, itin,
|
|
opc, asm, "", pattern> {
|
|
let Inst{4} = 0;
|
|
let Inst{7} = 1;
|
|
let Inst{20} = 0;
|
|
let Inst{27-21} = opcod;
|
|
}
|
|
|
|
// Extend instructions.
|
|
class AExtI<bits<8> opcod, dag oops, dag iops, InstrItinClass itin,
|
|
string opc, string asm, list<dag> pattern>
|
|
: I<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, ExtFrm, itin,
|
|
opc, asm, "", pattern> {
|
|
let Inst{7-4} = 0b0111;
|
|
let Inst{27-20} = opcod;
|
|
}
|
|
|
|
// Misc Arithmetic instructions.
|
|
class AMiscA1I<bits<8> opcod, dag oops, dag iops, InstrItinClass itin,
|
|
string opc, string asm, list<dag> pattern>
|
|
: I<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, ArithMiscFrm, itin,
|
|
opc, asm, "", pattern> {
|
|
let Inst{27-20} = opcod;
|
|
}
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
// ARMPat - Same as Pat<>, but requires that the compiler be in ARM mode.
|
|
class ARMPat<dag pattern, dag result> : Pat<pattern, result> {
|
|
list<Predicate> Predicates = [IsARM];
|
|
}
|
|
class ARMV5TEPat<dag pattern, dag result> : Pat<pattern, result> {
|
|
list<Predicate> Predicates = [IsARM, HasV5TE];
|
|
}
|
|
class ARMV6Pat<dag pattern, dag result> : Pat<pattern, result> {
|
|
list<Predicate> Predicates = [IsARM, HasV6];
|
|
}
|
|
class VFPPat<dag pattern, dag result> : Pat<pattern, result> {
|
|
list<Predicate> Predicates = [HasVFP2];
|
|
}
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
//
|
|
// Thumb Instruction Format Definitions.
|
|
//
|
|
|
|
// TI - Thumb instruction.
|
|
|
|
class ThumbI<dag oops, dag iops, AddrMode am, SizeFlagVal sz,
|
|
InstrItinClass itin, string asm, string cstr, list<dag> pattern>
|
|
: InstThumb<am, sz, IndexModeNone, ThumbFrm, GenericDomain, cstr, itin> {
|
|
let OutOperandList = oops;
|
|
let InOperandList = iops;
|
|
let AsmString = asm;
|
|
let Pattern = pattern;
|
|
list<Predicate> Predicates = [IsThumb];
|
|
}
|
|
|
|
class TI<dag oops, dag iops, InstrItinClass itin, string asm, list<dag> pattern>
|
|
: ThumbI<oops, iops, AddrModeNone, Size2Bytes, itin, asm, "", pattern>;
|
|
|
|
// Two-address instructions
|
|
class TIt<dag oops, dag iops, InstrItinClass itin, string asm, list<dag> pattern>
|
|
: ThumbI<oops, iops, AddrModeNone, Size2Bytes, itin, asm, "$lhs = $dst", pattern>;
|
|
|
|
// tBL, tBX 32-bit instructions
|
|
class TIx2<bits<5> opcod1, bits<2> opcod2, bit opcod3,
|
|
dag oops, dag iops, InstrItinClass itin, string asm, list<dag> pattern>
|
|
: ThumbI<oops, iops, AddrModeNone, Size4Bytes, itin, asm, "", pattern>, Encoding {
|
|
let Inst{31-27} = opcod1;
|
|
let Inst{15-14} = opcod2;
|
|
let Inst{12} = opcod3;
|
|
}
|
|
|
|
// BR_JT instructions
|
|
class TJTI<dag oops, dag iops, InstrItinClass itin, string asm, list<dag> pattern>
|
|
: ThumbI<oops, iops, AddrModeNone, SizeSpecial, itin, asm, "", pattern>;
|
|
|
|
// Thumb1 only
|
|
class Thumb1I<dag oops, dag iops, AddrMode am, SizeFlagVal sz,
|
|
InstrItinClass itin, string asm, string cstr, list<dag> pattern>
|
|
: InstThumb<am, sz, IndexModeNone, ThumbFrm, GenericDomain, cstr, itin> {
|
|
let OutOperandList = oops;
|
|
let InOperandList = iops;
|
|
let AsmString = asm;
|
|
let Pattern = pattern;
|
|
list<Predicate> Predicates = [IsThumb1Only];
|
|
}
|
|
|
|
class T1I<dag oops, dag iops, InstrItinClass itin,
|
|
string asm, list<dag> pattern>
|
|
: Thumb1I<oops, iops, AddrModeNone, Size2Bytes, itin, asm, "", pattern>;
|
|
class T1Ix2<dag oops, dag iops, InstrItinClass itin,
|
|
string asm, list<dag> pattern>
|
|
: Thumb1I<oops, iops, AddrModeNone, Size4Bytes, itin, asm, "", pattern>;
|
|
class T1JTI<dag oops, dag iops, InstrItinClass itin,
|
|
string asm, list<dag> pattern>
|
|
: Thumb1I<oops, iops, AddrModeNone, SizeSpecial, itin, asm, "", pattern>;
|
|
|
|
// Two-address instructions
|
|
class T1It<dag oops, dag iops, InstrItinClass itin,
|
|
string asm, string cstr, list<dag> pattern>
|
|
: Thumb1I<oops, iops, AddrModeNone, Size2Bytes, itin,
|
|
asm, cstr, pattern>;
|
|
|
|
// Thumb1 instruction that can either be predicated or set CPSR.
|
|
class Thumb1sI<dag oops, dag iops, AddrMode am, SizeFlagVal sz,
|
|
InstrItinClass itin,
|
|
string opc, string asm, string cstr, list<dag> pattern>
|
|
: InstThumb<am, sz, IndexModeNone, ThumbFrm, GenericDomain, cstr, itin> {
|
|
let OutOperandList = !con(oops, (outs s_cc_out:$s));
|
|
let InOperandList = !con(iops, (ins pred:$p));
|
|
let AsmString = !strconcat(opc, !strconcat("${s}${p}", asm));
|
|
let Pattern = pattern;
|
|
list<Predicate> Predicates = [IsThumb1Only];
|
|
}
|
|
|
|
class T1sI<dag oops, dag iops, InstrItinClass itin,
|
|
string opc, string asm, list<dag> pattern>
|
|
: Thumb1sI<oops, iops, AddrModeNone, Size2Bytes, itin, opc, asm, "", pattern>;
|
|
|
|
// Two-address instructions
|
|
class T1sIt<dag oops, dag iops, InstrItinClass itin,
|
|
string opc, string asm, list<dag> pattern>
|
|
: Thumb1sI<oops, iops, AddrModeNone, Size2Bytes, itin, opc, asm,
|
|
"$lhs = $dst", pattern>;
|
|
|
|
// Thumb1 instruction that can be predicated.
|
|
class Thumb1pI<dag oops, dag iops, AddrMode am, SizeFlagVal sz,
|
|
InstrItinClass itin,
|
|
string opc, string asm, string cstr, list<dag> pattern>
|
|
: InstThumb<am, sz, IndexModeNone, ThumbFrm, GenericDomain, cstr, itin> {
|
|
let OutOperandList = oops;
|
|
let InOperandList = !con(iops, (ins pred:$p));
|
|
let AsmString = !strconcat(opc, !strconcat("${p}", asm));
|
|
let Pattern = pattern;
|
|
list<Predicate> Predicates = [IsThumb1Only];
|
|
}
|
|
|
|
class T1pI<dag oops, dag iops, InstrItinClass itin,
|
|
string opc, string asm, list<dag> pattern>
|
|
: Thumb1pI<oops, iops, AddrModeNone, Size2Bytes, itin, opc, asm, "", pattern>;
|
|
|
|
// Two-address instructions
|
|
class T1pIt<dag oops, dag iops, InstrItinClass itin,
|
|
string opc, string asm, list<dag> pattern>
|
|
: Thumb1pI<oops, iops, AddrModeNone, Size2Bytes, itin, opc, asm,
|
|
"$lhs = $dst", pattern>;
|
|
|
|
class T1pI1<dag oops, dag iops, InstrItinClass itin,
|
|
string opc, string asm, list<dag> pattern>
|
|
: Thumb1pI<oops, iops, AddrModeT1_1, Size2Bytes, itin, opc, asm, "", pattern>;
|
|
class T1pI2<dag oops, dag iops, InstrItinClass itin,
|
|
string opc, string asm, list<dag> pattern>
|
|
: Thumb1pI<oops, iops, AddrModeT1_2, Size2Bytes, itin, opc, asm, "", pattern>;
|
|
class T1pI4<dag oops, dag iops, InstrItinClass itin,
|
|
string opc, string asm, list<dag> pattern>
|
|
: Thumb1pI<oops, iops, AddrModeT1_4, Size2Bytes, itin, opc, asm, "", pattern>;
|
|
class T1pIs<dag oops, dag iops,
|
|
InstrItinClass itin, string opc, string asm, list<dag> pattern>
|
|
: Thumb1pI<oops, iops, AddrModeT1_s, Size2Bytes, itin, opc, asm, "", pattern>;
|
|
|
|
class Encoding16 : Encoding {
|
|
let Inst{31-16} = 0x0000;
|
|
}
|
|
|
|
// A6.2 16-bit Thumb instruction encoding
|
|
class T1Encoding<bits<6> opcode> : Encoding16 {
|
|
let Inst{15-10} = opcode;
|
|
}
|
|
|
|
// A6.2.1 Shift (immediate), add, subtract, move, and compare encoding.
|
|
class T1General<bits<5> opcode> : Encoding16 {
|
|
let Inst{15-14} = 0b00;
|
|
let Inst{13-9} = opcode;
|
|
}
|
|
|
|
// A6.2.2 Data-processing encoding.
|
|
class T1DataProcessing<bits<4> opcode> : Encoding16 {
|
|
let Inst{15-10} = 0b010000;
|
|
let Inst{9-6} = opcode;
|
|
}
|
|
|
|
// A6.2.3 Special data instructions and branch and exchange encoding.
|
|
class T1Special<bits<4> opcode> : Encoding16 {
|
|
let Inst{15-10} = 0b010001;
|
|
let Inst{9-6} = opcode;
|
|
}
|
|
|
|
// A6.2.4 Load/store single data item encoding.
|
|
class T1LoadStore<bits<4> opA, bits<3> opB> : Encoding16 {
|
|
let Inst{15-12} = opA;
|
|
let Inst{11-9} = opB;
|
|
}
|
|
class T1LdSt<bits<3> opB> : T1LoadStore<0b0101, opB>;
|
|
class T1LdSt4Imm<bits<3> opB> : T1LoadStore<0b0110, opB>; // Immediate, 4 bytes
|
|
class T1LdSt1Imm<bits<3> opB> : T1LoadStore<0b0111, opB>; // Immediate, 1 byte
|
|
class T1LdSt2Imm<bits<3> opB> : T1LoadStore<0b1000, opB>; // Immediate, 2 bytes
|
|
class T1LdStSP<bits<3> opB> : T1LoadStore<0b1001, opB>; // SP relative
|
|
|
|
// A6.2.5 Miscellaneous 16-bit instructions encoding.
|
|
class T1Misc<bits<7> opcode> : Encoding16 {
|
|
let Inst{15-12} = 0b1011;
|
|
let Inst{11-5} = opcode;
|
|
}
|
|
|
|
// Thumb2I - Thumb2 instruction. Almost all Thumb2 instructions are predicable.
|
|
class Thumb2I<dag oops, dag iops, AddrMode am, SizeFlagVal sz,
|
|
InstrItinClass itin,
|
|
string opc, string asm, string cstr, list<dag> pattern>
|
|
: InstARM<am, sz, IndexModeNone, ThumbFrm, GenericDomain, cstr, itin> {
|
|
let OutOperandList = oops;
|
|
let InOperandList = !con(iops, (ins pred:$p));
|
|
let AsmString = !strconcat(opc, !strconcat("${p}", asm));
|
|
let Pattern = pattern;
|
|
list<Predicate> Predicates = [IsThumb2];
|
|
}
|
|
|
|
// Same as Thumb2I except it can optionally modify CPSR. Note it's modeled as
|
|
// an input operand since by default it's a zero register. It will
|
|
// become an implicit def once it's "flipped".
|
|
// FIXME: This uses unified syntax so {s} comes before {p}. We should make it
|
|
// more consistent.
|
|
class Thumb2sI<dag oops, dag iops, AddrMode am, SizeFlagVal sz,
|
|
InstrItinClass itin,
|
|
string opc, string asm, string cstr, list<dag> pattern>
|
|
: InstARM<am, sz, IndexModeNone, ThumbFrm, GenericDomain, cstr, itin> {
|
|
let OutOperandList = oops;
|
|
let InOperandList = !con(iops, (ins pred:$p, cc_out:$s));
|
|
let AsmString = !strconcat(opc, !strconcat("${s}${p}", asm));
|
|
let Pattern = pattern;
|
|
list<Predicate> Predicates = [IsThumb2];
|
|
}
|
|
|
|
// Special cases
|
|
class Thumb2XI<dag oops, dag iops, AddrMode am, SizeFlagVal sz,
|
|
InstrItinClass itin,
|
|
string asm, string cstr, list<dag> pattern>
|
|
: InstARM<am, sz, IndexModeNone, ThumbFrm, GenericDomain, cstr, itin> {
|
|
let OutOperandList = oops;
|
|
let InOperandList = iops;
|
|
let AsmString = asm;
|
|
let Pattern = pattern;
|
|
list<Predicate> Predicates = [IsThumb2];
|
|
}
|
|
|
|
class ThumbXI<dag oops, dag iops, AddrMode am, SizeFlagVal sz,
|
|
InstrItinClass itin,
|
|
string asm, string cstr, list<dag> pattern>
|
|
: InstARM<am, sz, IndexModeNone, ThumbFrm, GenericDomain, cstr, itin> {
|
|
let OutOperandList = oops;
|
|
let InOperandList = iops;
|
|
let AsmString = asm;
|
|
let Pattern = pattern;
|
|
list<Predicate> Predicates = [IsThumb1Only];
|
|
}
|
|
|
|
class T2I<dag oops, dag iops, InstrItinClass itin,
|
|
string opc, string asm, list<dag> pattern>
|
|
: Thumb2I<oops, iops, AddrModeNone, Size4Bytes, itin, opc, asm, "", pattern>;
|
|
class T2Ii12<dag oops, dag iops, InstrItinClass itin,
|
|
string opc, string asm, list<dag> pattern>
|
|
: Thumb2I<oops, iops, AddrModeT2_i12, Size4Bytes, itin, opc, asm, "", pattern>;
|
|
class T2Ii8<dag oops, dag iops, InstrItinClass itin,
|
|
string opc, string asm, list<dag> pattern>
|
|
: Thumb2I<oops, iops, AddrModeT2_i8, Size4Bytes, itin, opc, asm, "", pattern>;
|
|
class T2Iso<dag oops, dag iops, InstrItinClass itin,
|
|
string opc, string asm, list<dag> pattern>
|
|
: Thumb2I<oops, iops, AddrModeT2_so, Size4Bytes, itin, opc, asm, "", pattern>;
|
|
class T2Ipc<dag oops, dag iops, InstrItinClass itin,
|
|
string opc, string asm, list<dag> pattern>
|
|
: Thumb2I<oops, iops, AddrModeT2_pc, Size4Bytes, itin, opc, asm, "", pattern>;
|
|
class T2Ii8s4<bit P, bit W, bit load, dag oops, dag iops, InstrItinClass itin,
|
|
string opc, string asm, list<dag> pattern>
|
|
: Thumb2I<oops, iops, AddrModeT2_i8s4, Size4Bytes, itin, opc, asm, "",
|
|
pattern> {
|
|
let Inst{31-27} = 0b11101;
|
|
let Inst{26-25} = 0b00;
|
|
let Inst{24} = P;
|
|
let Inst{23} = ?; // The U bit.
|
|
let Inst{22} = 1;
|
|
let Inst{21} = W;
|
|
let Inst{20} = load;
|
|
}
|
|
|
|
class T2sI<dag oops, dag iops, InstrItinClass itin,
|
|
string opc, string asm, list<dag> pattern>
|
|
: Thumb2sI<oops, iops, AddrModeNone, Size4Bytes, itin, opc, asm, "", pattern>;
|
|
|
|
class T2XI<dag oops, dag iops, InstrItinClass itin,
|
|
string asm, list<dag> pattern>
|
|
: Thumb2XI<oops, iops, AddrModeNone, Size4Bytes, itin, asm, "", pattern>;
|
|
class T2JTI<dag oops, dag iops, InstrItinClass itin,
|
|
string asm, list<dag> pattern>
|
|
: Thumb2XI<oops, iops, AddrModeNone, SizeSpecial, itin, asm, "", pattern>;
|
|
|
|
class T2Ix2<dag oops, dag iops, InstrItinClass itin,
|
|
string opc, string asm, list<dag> pattern>
|
|
: Thumb2I<oops, iops, AddrModeNone, Size8Bytes, itin, opc, asm, "", pattern>;
|
|
|
|
// Two-address instructions
|
|
class T2XIt<dag oops, dag iops, InstrItinClass itin,
|
|
string asm, string cstr, list<dag> pattern>
|
|
: Thumb2XI<oops, iops, AddrModeNone, Size4Bytes, itin, asm, cstr, pattern>;
|
|
|
|
// T2Iidxldst - Thumb2 indexed load / store instructions.
|
|
class T2Iidxldst<bit signed, bits<2> opcod, bit load, bit pre,
|
|
dag oops, dag iops,
|
|
AddrMode am, IndexMode im, InstrItinClass itin,
|
|
string opc, string asm, string cstr, list<dag> pattern>
|
|
: InstARM<am, Size4Bytes, im, ThumbFrm, GenericDomain, cstr, itin> {
|
|
let OutOperandList = oops;
|
|
let InOperandList = !con(iops, (ins pred:$p));
|
|
let AsmString = !strconcat(opc, !strconcat("${p}", asm));
|
|
let Pattern = pattern;
|
|
list<Predicate> Predicates = [IsThumb2];
|
|
let Inst{31-27} = 0b11111;
|
|
let Inst{26-25} = 0b00;
|
|
let Inst{24} = signed;
|
|
let Inst{23} = 0;
|
|
let Inst{22-21} = opcod;
|
|
let Inst{20} = load;
|
|
let Inst{11} = 1;
|
|
// (P, W) = (1, 1) Pre-indexed or (0, 1) Post-indexed
|
|
let Inst{10} = pre; // The P bit.
|
|
let Inst{8} = 1; // The W bit.
|
|
}
|
|
|
|
// Helper class for disassembly only
|
|
// A6.3.16 & A6.3.17
|
|
// T2Imac - Thumb2 multiply [accumulate, and absolute difference] instructions.
|
|
class T2I_mac<bit long, bits<3> op22_20, bits<4> op7_4, dag oops, dag iops,
|
|
InstrItinClass itin, string opc, string asm, list<dag> pattern>
|
|
: T2I<oops, iops, itin, opc, asm, pattern> {
|
|
let Inst{31-27} = 0b11111;
|
|
let Inst{26-24} = 0b011;
|
|
let Inst{23} = long;
|
|
let Inst{22-20} = op22_20;
|
|
let Inst{7-4} = op7_4;
|
|
}
|
|
|
|
// Tv5Pat - Same as Pat<>, but requires V5T Thumb mode.
|
|
class Tv5Pat<dag pattern, dag result> : Pat<pattern, result> {
|
|
list<Predicate> Predicates = [IsThumb1Only, HasV5T];
|
|
}
|
|
|
|
// T1Pat - Same as Pat<>, but requires that the compiler be in Thumb1 mode.
|
|
class T1Pat<dag pattern, dag result> : Pat<pattern, result> {
|
|
list<Predicate> Predicates = [IsThumb1Only];
|
|
}
|
|
|
|
// T2Pat - Same as Pat<>, but requires that the compiler be in Thumb2 mode.
|
|
class T2Pat<dag pattern, dag result> : Pat<pattern, result> {
|
|
list<Predicate> Predicates = [IsThumb2];
|
|
}
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// ARM VFP Instruction templates.
|
|
//
|
|
|
|
// Almost all VFP instructions are predicable.
|
|
class VFPI<dag oops, dag iops, AddrMode am, SizeFlagVal sz,
|
|
IndexMode im, Format f, InstrItinClass itin,
|
|
string opc, string asm, string cstr, list<dag> pattern>
|
|
: InstARM<am, sz, im, f, VFPDomain, cstr, itin> {
|
|
let OutOperandList = oops;
|
|
let InOperandList = !con(iops, (ins pred:$p));
|
|
let AsmString = !strconcat(opc, !strconcat("${p}", asm));
|
|
let Pattern = pattern;
|
|
list<Predicate> Predicates = [HasVFP2];
|
|
}
|
|
|
|
// Special cases
|
|
class VFPXI<dag oops, dag iops, AddrMode am, SizeFlagVal sz,
|
|
IndexMode im, Format f, InstrItinClass itin,
|
|
string asm, string cstr, list<dag> pattern>
|
|
: InstARM<am, sz, im, f, VFPDomain, cstr, itin> {
|
|
let OutOperandList = oops;
|
|
let InOperandList = iops;
|
|
let AsmString = asm;
|
|
let Pattern = pattern;
|
|
list<Predicate> Predicates = [HasVFP2];
|
|
}
|
|
|
|
class VFPAI<dag oops, dag iops, Format f, InstrItinClass itin,
|
|
string opc, string asm, list<dag> pattern>
|
|
: VFPI<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, f, itin,
|
|
opc, asm, "", pattern>;
|
|
|
|
// ARM VFP addrmode5 loads and stores
|
|
class ADI5<bits<4> opcod1, bits<2> opcod2, dag oops, dag iops,
|
|
InstrItinClass itin,
|
|
string opc, string asm, list<dag> pattern>
|
|
: VFPI<oops, iops, AddrMode5, Size4Bytes, IndexModeNone,
|
|
VFPLdStFrm, itin, opc, asm, "", pattern> {
|
|
// TODO: Mark the instructions with the appropriate subtarget info.
|
|
let Inst{27-24} = opcod1;
|
|
let Inst{21-20} = opcod2;
|
|
let Inst{11-8} = 0b1011;
|
|
|
|
// 64-bit loads & stores operate on both NEON and VFP pipelines.
|
|
let Dom = VFPNeonDomain.Value;
|
|
}
|
|
|
|
class ASI5<bits<4> opcod1, bits<2> opcod2, dag oops, dag iops,
|
|
InstrItinClass itin,
|
|
string opc, string asm, list<dag> pattern>
|
|
: VFPI<oops, iops, AddrMode5, Size4Bytes, IndexModeNone,
|
|
VFPLdStFrm, itin, opc, asm, "", pattern> {
|
|
// TODO: Mark the instructions with the appropriate subtarget info.
|
|
let Inst{27-24} = opcod1;
|
|
let Inst{21-20} = opcod2;
|
|
let Inst{11-8} = 0b1010;
|
|
}
|
|
|
|
// Load / store multiple
|
|
class AXDI5<dag oops, dag iops, IndexMode im, InstrItinClass itin,
|
|
string asm, string cstr, list<dag> pattern>
|
|
: VFPXI<oops, iops, AddrMode5, Size4Bytes, im,
|
|
VFPLdStMulFrm, itin, asm, cstr, pattern> {
|
|
// TODO: Mark the instructions with the appropriate subtarget info.
|
|
let Inst{27-25} = 0b110;
|
|
let Inst{11-8} = 0b1011;
|
|
|
|
// 64-bit loads & stores operate on both NEON and VFP pipelines.
|
|
let Dom = VFPNeonDomain.Value;
|
|
}
|
|
|
|
class AXSI5<dag oops, dag iops, IndexMode im, InstrItinClass itin,
|
|
string asm, string cstr, list<dag> pattern>
|
|
: VFPXI<oops, iops, AddrMode5, Size4Bytes, im,
|
|
VFPLdStMulFrm, itin, asm, cstr, pattern> {
|
|
// TODO: Mark the instructions with the appropriate subtarget info.
|
|
let Inst{27-25} = 0b110;
|
|
let Inst{11-8} = 0b1010;
|
|
}
|
|
|
|
// Double precision, unary
|
|
class ADuI<bits<5> opcod1, bits<2> opcod2, bits<4> opcod3, bits<2> opcod4,
|
|
bit opcod5, dag oops, dag iops, InstrItinClass itin, string opc,
|
|
string asm, list<dag> pattern>
|
|
: VFPAI<oops, iops, VFPUnaryFrm, itin, opc, asm, pattern> {
|
|
let Inst{27-23} = opcod1;
|
|
let Inst{21-20} = opcod2;
|
|
let Inst{19-16} = opcod3;
|
|
let Inst{11-8} = 0b1011;
|
|
let Inst{7-6} = opcod4;
|
|
let Inst{4} = opcod5;
|
|
}
|
|
|
|
// Double precision, binary
|
|
class ADbI<bits<5> opcod1, bits<2> opcod2, bit op6, bit op4, dag oops,
|
|
dag iops, InstrItinClass itin, string opc, string asm, list<dag> pattern>
|
|
: VFPAI<oops, iops, VFPBinaryFrm, itin, opc, asm, pattern> {
|
|
let Inst{27-23} = opcod1;
|
|
let Inst{21-20} = opcod2;
|
|
let Inst{11-8} = 0b1011;
|
|
let Inst{6} = op6;
|
|
let Inst{4} = op4;
|
|
}
|
|
|
|
// Single precision, unary
|
|
class ASuI<bits<5> opcod1, bits<2> opcod2, bits<4> opcod3, bits<2> opcod4,
|
|
bit opcod5, dag oops, dag iops, InstrItinClass itin, string opc,
|
|
string asm, list<dag> pattern>
|
|
: VFPAI<oops, iops, VFPUnaryFrm, itin, opc, asm, pattern> {
|
|
let Inst{27-23} = opcod1;
|
|
let Inst{21-20} = opcod2;
|
|
let Inst{19-16} = opcod3;
|
|
let Inst{11-8} = 0b1010;
|
|
let Inst{7-6} = opcod4;
|
|
let Inst{4} = opcod5;
|
|
}
|
|
|
|
// Single precision unary, if no NEON
|
|
// Same as ASuI except not available if NEON is enabled
|
|
class ASuIn<bits<5> opcod1, bits<2> opcod2, bits<4> opcod3, bits<2> opcod4,
|
|
bit opcod5, dag oops, dag iops, InstrItinClass itin, string opc,
|
|
string asm, list<dag> pattern>
|
|
: ASuI<opcod1, opcod2, opcod3, opcod4, opcod5, oops, iops, itin, opc, asm,
|
|
pattern> {
|
|
list<Predicate> Predicates = [HasVFP2,DontUseNEONForFP];
|
|
}
|
|
|
|
// Single precision, binary
|
|
class ASbI<bits<5> opcod1, bits<2> opcod2, bit op6, bit op4, dag oops, dag iops,
|
|
InstrItinClass itin, string opc, string asm, list<dag> pattern>
|
|
: VFPAI<oops, iops, VFPBinaryFrm, itin, opc, asm, pattern> {
|
|
let Inst{27-23} = opcod1;
|
|
let Inst{21-20} = opcod2;
|
|
let Inst{11-8} = 0b1010;
|
|
let Inst{6} = op6;
|
|
let Inst{4} = op4;
|
|
}
|
|
|
|
// Single precision binary, if no NEON
|
|
// Same as ASbI except not available if NEON is enabled
|
|
class ASbIn<bits<5> opcod1, bits<2> opcod2, bit op6, bit op4, dag oops,
|
|
dag iops, InstrItinClass itin, string opc, string asm, list<dag> pattern>
|
|
: ASbI<opcod1, opcod2, op6, op4, oops, iops, itin, opc, asm, pattern> {
|
|
list<Predicate> Predicates = [HasVFP2,DontUseNEONForFP];
|
|
}
|
|
|
|
// VFP conversion instructions
|
|
class AVConv1I<bits<5> opcod1, bits<2> opcod2, bits<4> opcod3, bits<4> opcod4,
|
|
dag oops, dag iops, InstrItinClass itin, string opc, string asm,
|
|
list<dag> pattern>
|
|
: VFPAI<oops, iops, VFPConv1Frm, itin, opc, asm, pattern> {
|
|
let Inst{27-23} = opcod1;
|
|
let Inst{21-20} = opcod2;
|
|
let Inst{19-16} = opcod3;
|
|
let Inst{11-8} = opcod4;
|
|
let Inst{6} = 1;
|
|
let Inst{4} = 0;
|
|
}
|
|
|
|
// VFP conversion between floating-point and fixed-point
|
|
class AVConv1XI<bits<5> op1, bits<2> op2, bits<4> op3, bits<4> op4, bit op5,
|
|
dag oops, dag iops, InstrItinClass itin, string opc, string asm,
|
|
list<dag> pattern>
|
|
: AVConv1I<op1, op2, op3, op4, oops, iops, itin, opc, asm, pattern> {
|
|
// size (fixed-point number): sx == 0 ? 16 : 32
|
|
let Inst{7} = op5; // sx
|
|
}
|
|
|
|
// VFP conversion instructions, if no NEON
|
|
class AVConv1In<bits<5> opcod1, bits<2> opcod2, bits<4> opcod3, bits<4> opcod4,
|
|
dag oops, dag iops, InstrItinClass itin,
|
|
string opc, string asm, list<dag> pattern>
|
|
: AVConv1I<opcod1, opcod2, opcod3, opcod4, oops, iops, itin, opc, asm,
|
|
pattern> {
|
|
list<Predicate> Predicates = [HasVFP2,DontUseNEONForFP];
|
|
}
|
|
|
|
class AVConvXI<bits<8> opcod1, bits<4> opcod2, dag oops, dag iops, Format f,
|
|
InstrItinClass itin,
|
|
string opc, string asm, list<dag> pattern>
|
|
: VFPAI<oops, iops, f, itin, opc, asm, pattern> {
|
|
let Inst{27-20} = opcod1;
|
|
let Inst{11-8} = opcod2;
|
|
let Inst{4} = 1;
|
|
}
|
|
|
|
class AVConv2I<bits<8> opcod1, bits<4> opcod2, dag oops, dag iops,
|
|
InstrItinClass itin, string opc, string asm, list<dag> pattern>
|
|
: AVConvXI<opcod1, opcod2, oops, iops, VFPConv2Frm, itin, opc, asm, pattern>;
|
|
|
|
class AVConv3I<bits<8> opcod1, bits<4> opcod2, dag oops, dag iops,
|
|
InstrItinClass itin, string opc, string asm, list<dag> pattern>
|
|
: AVConvXI<opcod1, opcod2, oops, iops, VFPConv3Frm, itin, opc, asm, pattern>;
|
|
|
|
class AVConv4I<bits<8> opcod1, bits<4> opcod2, dag oops, dag iops,
|
|
InstrItinClass itin, string opc, string asm, list<dag> pattern>
|
|
: AVConvXI<opcod1, opcod2, oops, iops, VFPConv4Frm, itin, opc, asm, pattern>;
|
|
|
|
class AVConv5I<bits<8> opcod1, bits<4> opcod2, dag oops, dag iops,
|
|
InstrItinClass itin, string opc, string asm, list<dag> pattern>
|
|
: AVConvXI<opcod1, opcod2, oops, iops, VFPConv5Frm, itin, opc, asm, pattern>;
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// ARM NEON Instruction templates.
|
|
//
|
|
|
|
class NeonI<dag oops, dag iops, AddrMode am, IndexMode im, InstrItinClass itin,
|
|
string opc, string dt, string asm, string cstr, list<dag> pattern>
|
|
: InstARM<am, Size4Bytes, im, NEONFrm, NeonDomain, cstr, itin> {
|
|
let OutOperandList = oops;
|
|
let InOperandList = !con(iops, (ins pred:$p));
|
|
let AsmString = !strconcat(
|
|
!strconcat(!strconcat(opc, "${p}"), !strconcat(".", dt)),
|
|
!strconcat("\t", asm));
|
|
let Pattern = pattern;
|
|
list<Predicate> Predicates = [HasNEON];
|
|
}
|
|
|
|
// Same as NeonI except it does not have a "data type" specifier.
|
|
class NeonXI<dag oops, dag iops, AddrMode am, IndexMode im, InstrItinClass itin,
|
|
string opc, string asm, string cstr, list<dag> pattern>
|
|
: InstARM<am, Size4Bytes, im, NEONFrm, NeonDomain, cstr, itin> {
|
|
let OutOperandList = oops;
|
|
let InOperandList = !con(iops, (ins pred:$p));
|
|
let AsmString = !strconcat(!strconcat(opc, "${p}"), !strconcat("\t", asm));
|
|
let Pattern = pattern;
|
|
list<Predicate> Predicates = [HasNEON];
|
|
}
|
|
|
|
class NI<dag oops, dag iops, InstrItinClass itin, string opc, string asm,
|
|
list<dag> pattern>
|
|
: NeonXI<oops, iops, AddrModeNone, IndexModeNone, itin, opc, asm, "",
|
|
pattern> {
|
|
}
|
|
|
|
class NI4<dag oops, dag iops, InstrItinClass itin, string opc,
|
|
string asm, list<dag> pattern>
|
|
: NeonXI<oops, iops, AddrMode4, IndexModeNone, itin, opc, asm, "",
|
|
pattern> {
|
|
}
|
|
|
|
class NLdSt<bit op23, bits<2> op21_20, bits<4> op11_8, bits<4> op7_4,
|
|
dag oops, dag iops, InstrItinClass itin,
|
|
string opc, string dt, string asm, string cstr, list<dag> pattern>
|
|
: NeonI<oops, iops, AddrMode6, IndexModeNone, itin, opc, dt, asm, cstr,
|
|
pattern> {
|
|
let Inst{31-24} = 0b11110100;
|
|
let Inst{23} = op23;
|
|
let Inst{21-20} = op21_20;
|
|
let Inst{11-8} = op11_8;
|
|
let Inst{7-4} = op7_4;
|
|
}
|
|
|
|
class NDataI<dag oops, dag iops, InstrItinClass itin,
|
|
string opc, string dt, string asm, string cstr, list<dag> pattern>
|
|
: NeonI<oops, iops, AddrModeNone, IndexModeNone, itin, opc, dt, asm,
|
|
cstr, pattern> {
|
|
let Inst{31-25} = 0b1111001;
|
|
}
|
|
|
|
class NDataXI<dag oops, dag iops, InstrItinClass itin,
|
|
string opc, string asm, string cstr, list<dag> pattern>
|
|
: NeonXI<oops, iops, AddrModeNone, IndexModeNone, itin, opc, asm,
|
|
cstr, pattern> {
|
|
let Inst{31-25} = 0b1111001;
|
|
}
|
|
|
|
// NEON "one register and a modified immediate" format.
|
|
class N1ModImm<bit op23, bits<3> op21_19, bits<4> op11_8, bit op7, bit op6,
|
|
bit op5, bit op4,
|
|
dag oops, dag iops, InstrItinClass itin,
|
|
string opc, string dt, string asm, string cstr, list<dag> pattern>
|
|
: NDataI<oops, iops, itin, opc, dt, asm, cstr, pattern> {
|
|
let Inst{23} = op23;
|
|
let Inst{21-19} = op21_19;
|
|
let Inst{11-8} = op11_8;
|
|
let Inst{7} = op7;
|
|
let Inst{6} = op6;
|
|
let Inst{5} = op5;
|
|
let Inst{4} = op4;
|
|
}
|
|
|
|
// NEON 2 vector register format.
|
|
class N2V<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18, bits<2> op17_16,
|
|
bits<5> op11_7, bit op6, bit op4,
|
|
dag oops, dag iops, InstrItinClass itin,
|
|
string opc, string dt, string asm, string cstr, list<dag> pattern>
|
|
: NDataI<oops, iops, itin, opc, dt, asm, cstr, pattern> {
|
|
let Inst{24-23} = op24_23;
|
|
let Inst{21-20} = op21_20;
|
|
let Inst{19-18} = op19_18;
|
|
let Inst{17-16} = op17_16;
|
|
let Inst{11-7} = op11_7;
|
|
let Inst{6} = op6;
|
|
let Inst{4} = op4;
|
|
}
|
|
|
|
// Same as N2V except it doesn't have a datatype suffix.
|
|
class N2VX<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18, bits<2> op17_16,
|
|
bits<5> op11_7, bit op6, bit op4,
|
|
dag oops, dag iops, InstrItinClass itin,
|
|
string opc, string asm, string cstr, list<dag> pattern>
|
|
: NDataXI<oops, iops, itin, opc, asm, cstr, pattern> {
|
|
let Inst{24-23} = op24_23;
|
|
let Inst{21-20} = op21_20;
|
|
let Inst{19-18} = op19_18;
|
|
let Inst{17-16} = op17_16;
|
|
let Inst{11-7} = op11_7;
|
|
let Inst{6} = op6;
|
|
let Inst{4} = op4;
|
|
}
|
|
|
|
// NEON 2 vector register with immediate.
|
|
class N2VImm<bit op24, bit op23, bits<4> op11_8, bit op7, bit op6, bit op4,
|
|
dag oops, dag iops, InstrItinClass itin,
|
|
string opc, string dt, string asm, string cstr, list<dag> pattern>
|
|
: NDataI<oops, iops, itin, opc, dt, asm, cstr, pattern> {
|
|
let Inst{24} = op24;
|
|
let Inst{23} = op23;
|
|
let Inst{11-8} = op11_8;
|
|
let Inst{7} = op7;
|
|
let Inst{6} = op6;
|
|
let Inst{4} = op4;
|
|
}
|
|
|
|
// NEON 3 vector register format.
|
|
class N3V<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op6, bit op4,
|
|
dag oops, dag iops, InstrItinClass itin,
|
|
string opc, string dt, string asm, string cstr, list<dag> pattern>
|
|
: NDataI<oops, iops, itin, opc, dt, asm, cstr, pattern> {
|
|
let Inst{24} = op24;
|
|
let Inst{23} = op23;
|
|
let Inst{21-20} = op21_20;
|
|
let Inst{11-8} = op11_8;
|
|
let Inst{6} = op6;
|
|
let Inst{4} = op4;
|
|
}
|
|
|
|
// Same as N3VX except it doesn't have a data type suffix.
|
|
class N3VX<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op6, bit op4,
|
|
dag oops, dag iops, InstrItinClass itin,
|
|
string opc, string asm, string cstr, list<dag> pattern>
|
|
: NDataXI<oops, iops, itin, opc, asm, cstr, pattern> {
|
|
let Inst{24} = op24;
|
|
let Inst{23} = op23;
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let Inst{21-20} = op21_20;
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|
let Inst{11-8} = op11_8;
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|
let Inst{6} = op6;
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|
let Inst{4} = op4;
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|
}
|
|
|
|
// NEON VMOVs between scalar and core registers.
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|
class NVLaneOp<bits<8> opcod1, bits<4> opcod2, bits<2> opcod3,
|
|
dag oops, dag iops, Format f, InstrItinClass itin,
|
|
string opc, string dt, string asm, list<dag> pattern>
|
|
: InstARM<AddrModeNone, Size4Bytes, IndexModeNone, f, GenericDomain,
|
|
"", itin> {
|
|
let Inst{27-20} = opcod1;
|
|
let Inst{11-8} = opcod2;
|
|
let Inst{6-5} = opcod3;
|
|
let Inst{4} = 1;
|
|
|
|
let OutOperandList = oops;
|
|
let InOperandList = !con(iops, (ins pred:$p));
|
|
let AsmString = !strconcat(
|
|
!strconcat(!strconcat(opc, "${p}"), !strconcat(".", dt)),
|
|
!strconcat("\t", asm));
|
|
let Pattern = pattern;
|
|
list<Predicate> Predicates = [HasNEON];
|
|
}
|
|
class NVGetLane<bits<8> opcod1, bits<4> opcod2, bits<2> opcod3,
|
|
dag oops, dag iops, InstrItinClass itin,
|
|
string opc, string dt, string asm, list<dag> pattern>
|
|
: NVLaneOp<opcod1, opcod2, opcod3, oops, iops, NEONGetLnFrm, itin,
|
|
opc, dt, asm, pattern>;
|
|
class NVSetLane<bits<8> opcod1, bits<4> opcod2, bits<2> opcod3,
|
|
dag oops, dag iops, InstrItinClass itin,
|
|
string opc, string dt, string asm, list<dag> pattern>
|
|
: NVLaneOp<opcod1, opcod2, opcod3, oops, iops, NEONSetLnFrm, itin,
|
|
opc, dt, asm, pattern>;
|
|
class NVDup<bits<8> opcod1, bits<4> opcod2, bits<2> opcod3,
|
|
dag oops, dag iops, InstrItinClass itin,
|
|
string opc, string dt, string asm, list<dag> pattern>
|
|
: NVLaneOp<opcod1, opcod2, opcod3, oops, iops, NEONDupFrm, itin,
|
|
opc, dt, asm, pattern>;
|
|
|
|
// NEONFPPat - Same as Pat<>, but requires that the compiler be using NEON
|
|
// for single-precision FP.
|
|
class NEONFPPat<dag pattern, dag result> : Pat<pattern, result> {
|
|
list<Predicate> Predicates = [HasNEON,UseNEONForFP];
|
|
}
|