llvm-6502/lib/Target/Sparc
Chandler Carruth 81fd0ba8ab Actually finish switching to the new system for Target sublibrary
TableGen deps introduced in r136023. This completes the fixing that
dgregor started in r136621. Sorry for missing these the first time
around.

This should fix some of the random race-condition failures people are
still seeing with CMake.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136643 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-01 19:55:11 +00:00
..
MCTargetDesc Rewrite the CMake build to use explicit dependencies between libraries, 2011-07-29 00:14:25 +00:00
TargetInfo Actually finish switching to the new system for Target sublibrary 2011-08-01 19:55:11 +00:00
CMakeLists.txt Rewrite the CMake build to use explicit dependencies between libraries, 2011-07-29 00:14:25 +00:00
DelaySlotFiller.cpp - Rename TargetInstrDesc, TargetOperandInfo to MCInstrDesc and MCOperandInfo and 2011-06-28 19:10:37 +00:00
FPMover.cpp
Makefile Next round of MC refactoring. This patch factor MC table instantiations, MC 2011-07-14 20:59:42 +00:00
README.txt
Sparc.h Next round of MC refactoring. This patch factor MC table instantiations, MC 2011-07-14 20:59:42 +00:00
Sparc.td
SparcAsmPrinter.cpp
SparcCallingConv.td
SparcFrameLowering.cpp
SparcFrameLowering.h
SparcInstrFormats.td
SparcInstrInfo.cpp Next round of MC refactoring. This patch factor MC table instantiations, MC 2011-07-14 20:59:42 +00:00
SparcInstrInfo.h Hide the call to InitMCInstrInfo into tblgen generated ctor. 2011-07-01 17:57:27 +00:00
SparcInstrInfo.td
SparcISelDAGToDAG.cpp
SparcISelLowering.cpp Code generation for 'fence' instruction. 2011-07-27 22:21:52 +00:00
SparcISelLowering.h Remove getRegClassForInlineAsmConstraint from sparc. 2011-06-29 18:53:10 +00:00
SparcMachineFunctionInfo.h
SparcRegisterInfo.cpp Move getInitialFrameState from TargetFrameInfo to MCAsmInfo (suggestions for 2011-07-18 22:29:13 +00:00
SparcRegisterInfo.h Sink getDwarfRegNum, getLLVMRegNum, getSEHRegNum from TargetRegisterInfo down 2011-07-18 20:57:22 +00:00
SparcRegisterInfo.td Use set operations instead of plain lists to enumerate register classes. 2011-06-15 23:28:14 +00:00
SparcSelectionDAGInfo.cpp
SparcSelectionDAGInfo.h
SparcSubtarget.cpp Next round of MC refactoring. This patch factor MC table instantiations, MC 2011-07-14 20:59:42 +00:00
SparcSubtarget.h Compute feature bits at time of MCSubtargetInfo initialization. 2011-07-07 07:07:08 +00:00
SparcTargetMachine.cpp - Move CodeModel from a TargetMachine global option to MCCodeGenInfo. 2011-07-20 07:51:56 +00:00
SparcTargetMachine.h - Move CodeModel from a TargetMachine global option to MCCodeGenInfo. 2011-07-20 07:51:56 +00:00

To-do
-----

* Keep the address of the constant pool in a register instead of forming its
  address all of the time.
* We can fold small constant offsets into the %hi/%lo references to constant
  pool addresses as well.
* When in V9 mode, register allocate %icc[0-3].
* Add support for isel'ing UMUL_LOHI instead of marking it as Expand.
* Emit the 'Branch on Integer Register with Prediction' instructions.  It's
  not clear how to write a pattern for this though:

float %t1(int %a, int* %p) {
        %C = seteq int %a, 0
        br bool %C, label %T, label %F
T:
        store int 123, int* %p
        br label %F
F:
        ret float undef
}

codegens to this:

t1:
        save -96, %o6, %o6
1)      subcc %i0, 0, %l0
1)      bne .LBBt1_2    ! F
        nop
.LBBt1_1:       ! T
        or %g0, 123, %l0
        st %l0, [%i1]
.LBBt1_2:       ! F
        restore %g0, %g0, %g0
        retl
        nop

1) should be replaced with a brz in V9 mode.

* Same as above, but emit conditional move on register zero (p192) in V9 
  mode.  Testcase:

int %t1(int %a, int %b) {
        %C = seteq int %a, 0
        %D = select bool %C, int %a, int %b
        ret int %D
}

* Emit MULX/[SU]DIVX instructions in V9 mode instead of fiddling 
  with the Y register, if they are faster.

* Codegen bswap(load)/store(bswap) -> load/store ASI

* Implement frame pointer elimination, e.g. eliminate save/restore for 
  leaf fns.
* Fill delay slots

* Implement JIT support