mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-07-26 06:29:20 +00:00
3d47855394
So there are a couple of issues with indirect calls on thumbv4t. First, the most 'obvious' instruction, 'blx' isn't available until v5t. And secondly, the next-most-obvious sequence: 'mov lr, pc; bx rN' doesn't DTRT in thumb code because the saved off pc has its thumb bit cleared, so when the callee returns we end up in ARM mode.... yuck. The solution is to 'bl' to a nearby landing pad with a 'bx rN' in it. We could cut down on code size by sharing the landing pads between call sites that are close enough, but for the moment let's do correctness first and look at performance later. Patch by: Iain Sandoe http://reviews.llvm.org/D6519 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@223380 91177308-0d34-0410-b5e6-96231b3b80d8
26 lines
771 B
LLVM
26 lines
771 B
LLVM
; RUN: llc -mtriple=thumb-none-macho -mcpu=arm7tdmi %s -o - | FileCheck %s
|
|
; RUN: llc -mtriple=thumb-none-macho -mcpu=arm7tdmi %s -filetype=obj -o /dev/null
|
|
|
|
declare void @callee()
|
|
|
|
define void @test_call() {
|
|
; BX can only take a register before v5t came along, so we must materialise
|
|
; the address properly.
|
|
; CHECK-LABEL: test_call:
|
|
; CHECK: ldr r[[CALLEE_STUB:[0-9]+]], [[LITPOOL:LCPI[0-9]+_[0-9]+]]
|
|
; CHECK: [[PC_LABEL:LPC[0-9]+_[0-9]+]]:
|
|
; CHECK-NEXT: add r[[CALLEE_STUB]], pc
|
|
; CHECK: ldr [[CALLEE:r[0-9]+]], [r[[CALLEE_STUB]]]
|
|
; CHECK-NOT: mov lr, pc
|
|
; CHECK: bl [[INDIRECT_PAD:Ltmp[0-9]+]]
|
|
|
|
; CHECK: [[LITPOOL]]:
|
|
; CHECK-NEXT: .long L_callee$non_lazy_ptr-([[PC_LABEL]]+4)
|
|
|
|
; CHECK: [[INDIRECT_PAD]]:
|
|
; CHECK: bx [[CALLEE]]
|
|
|
|
call void @callee()
|
|
ret void
|
|
}
|