mirror of
https://github.com/c64scene-ar/llvm-6502.git
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8239daf7c8
1. Fix pre-ra scheduler so it doesn't try to push instructions above calls to "optimize for latency". Call instructions don't have the right latency and this is more likely to use introduce spills. 2. Fix if-converter cost function. For ARM, it should use instruction latencies, not # of micro-ops since multi-latency instructions is completely executed even when the predicate is false. Also, some instruction will be "slower" when they are predicated due to the register def becoming implicit input. rdar://8598427 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118135 91177308-0d34-0410-b5e6-96231b3b80d8
686 lines
26 KiB
C++
686 lines
26 KiB
C++
//===------- llvm/CodeGen/ScheduleDAG.h - Common Base Class------*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file implements the ScheduleDAG class, which is used as the common
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// base class for instruction schedulers.
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_CODEGEN_SCHEDULEDAG_H
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#define LLVM_CODEGEN_SCHEDULEDAG_H
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#include "llvm/CodeGen/MachineBasicBlock.h"
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#include "llvm/Target/TargetMachine.h"
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#include "llvm/ADT/DenseMap.h"
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#include "llvm/ADT/BitVector.h"
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#include "llvm/ADT/GraphTraits.h"
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#include "llvm/ADT/SmallVector.h"
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#include "llvm/ADT/PointerIntPair.h"
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namespace llvm {
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class AliasAnalysis;
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class SUnit;
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class MachineConstantPool;
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class MachineFunction;
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class MachineRegisterInfo;
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class MachineInstr;
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class TargetRegisterInfo;
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class ScheduleDAG;
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class SDNode;
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class TargetInstrInfo;
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class TargetInstrDesc;
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class TargetMachine;
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class TargetRegisterClass;
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template<class Graph> class GraphWriter;
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/// SDep - Scheduling dependency. This represents one direction of an
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/// edge in the scheduling DAG.
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class SDep {
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public:
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/// Kind - These are the different kinds of scheduling dependencies.
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enum Kind {
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Data, ///< Regular data dependence (aka true-dependence).
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Anti, ///< A register anti-dependedence (aka WAR).
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Output, ///< A register output-dependence (aka WAW).
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Order ///< Any other ordering dependency.
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};
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private:
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/// Dep - A pointer to the depending/depended-on SUnit, and an enum
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/// indicating the kind of the dependency.
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PointerIntPair<SUnit *, 2, Kind> Dep;
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/// Contents - A union discriminated by the dependence kind.
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union {
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/// Reg - For Data, Anti, and Output dependencies, the associated
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/// register. For Data dependencies that don't currently have a register
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/// assigned, this is set to zero.
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unsigned Reg;
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/// Order - Additional information about Order dependencies.
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struct {
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/// isNormalMemory - True if both sides of the dependence
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/// access memory in non-volatile and fully modeled ways.
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bool isNormalMemory : 1;
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/// isMustAlias - True if both sides of the dependence are known to
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/// access the same memory.
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bool isMustAlias : 1;
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/// isArtificial - True if this is an artificial dependency, meaning
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/// it is not necessary for program correctness, and may be safely
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/// deleted if necessary.
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bool isArtificial : 1;
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} Order;
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} Contents;
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/// Latency - The time associated with this edge. Often this is just
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/// the value of the Latency field of the predecessor, however advanced
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/// models may provide additional information about specific edges.
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unsigned Latency;
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public:
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/// SDep - Construct a null SDep. This is only for use by container
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/// classes which require default constructors. SUnits may not
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/// have null SDep edges.
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SDep() : Dep(0, Data) {}
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/// SDep - Construct an SDep with the specified values.
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SDep(SUnit *S, Kind kind, unsigned latency = 1, unsigned Reg = 0,
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bool isNormalMemory = false, bool isMustAlias = false,
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bool isArtificial = false)
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: Dep(S, kind), Contents(), Latency(latency) {
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switch (kind) {
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case Anti:
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case Output:
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assert(Reg != 0 &&
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"SDep::Anti and SDep::Output must use a non-zero Reg!");
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// fall through
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case Data:
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assert(!isMustAlias && "isMustAlias only applies with SDep::Order!");
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assert(!isArtificial && "isArtificial only applies with SDep::Order!");
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Contents.Reg = Reg;
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break;
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case Order:
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assert(Reg == 0 && "Reg given for non-register dependence!");
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Contents.Order.isNormalMemory = isNormalMemory;
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Contents.Order.isMustAlias = isMustAlias;
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Contents.Order.isArtificial = isArtificial;
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break;
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}
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}
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bool operator==(const SDep &Other) const {
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if (Dep != Other.Dep || Latency != Other.Latency) return false;
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switch (Dep.getInt()) {
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case Data:
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case Anti:
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case Output:
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return Contents.Reg == Other.Contents.Reg;
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case Order:
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return Contents.Order.isNormalMemory ==
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Other.Contents.Order.isNormalMemory &&
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Contents.Order.isMustAlias == Other.Contents.Order.isMustAlias &&
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Contents.Order.isArtificial == Other.Contents.Order.isArtificial;
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}
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assert(0 && "Invalid dependency kind!");
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return false;
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}
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bool operator!=(const SDep &Other) const {
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return !operator==(Other);
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}
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/// getLatency - Return the latency value for this edge, which roughly
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/// means the minimum number of cycles that must elapse between the
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/// predecessor and the successor, given that they have this edge
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/// between them.
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unsigned getLatency() const {
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return Latency;
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}
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/// setLatency - Set the latency for this edge.
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void setLatency(unsigned Lat) {
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Latency = Lat;
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}
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//// getSUnit - Return the SUnit to which this edge points.
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SUnit *getSUnit() const {
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return Dep.getPointer();
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}
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//// setSUnit - Assign the SUnit to which this edge points.
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void setSUnit(SUnit *SU) {
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Dep.setPointer(SU);
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}
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/// getKind - Return an enum value representing the kind of the dependence.
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Kind getKind() const {
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return Dep.getInt();
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}
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/// isCtrl - Shorthand for getKind() != SDep::Data.
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bool isCtrl() const {
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return getKind() != Data;
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}
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/// isNormalMemory - Test if this is an Order dependence between two
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/// memory accesses where both sides of the dependence access memory
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/// in non-volatile and fully modeled ways.
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bool isNormalMemory() const {
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return getKind() == Order && Contents.Order.isNormalMemory;
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}
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/// isMustAlias - Test if this is an Order dependence that is marked
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/// as "must alias", meaning that the SUnits at either end of the edge
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/// have a memory dependence on a known memory location.
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bool isMustAlias() const {
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return getKind() == Order && Contents.Order.isMustAlias;
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}
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/// isArtificial - Test if this is an Order dependence that is marked
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/// as "artificial", meaning it isn't necessary for correctness.
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bool isArtificial() const {
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return getKind() == Order && Contents.Order.isArtificial;
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}
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/// isAssignedRegDep - Test if this is a Data dependence that is
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/// associated with a register.
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bool isAssignedRegDep() const {
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return getKind() == Data && Contents.Reg != 0;
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}
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/// getReg - Return the register associated with this edge. This is
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/// only valid on Data, Anti, and Output edges. On Data edges, this
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/// value may be zero, meaning there is no associated register.
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unsigned getReg() const {
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assert((getKind() == Data || getKind() == Anti || getKind() == Output) &&
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"getReg called on non-register dependence edge!");
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return Contents.Reg;
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}
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/// setReg - Assign the associated register for this edge. This is
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/// only valid on Data, Anti, and Output edges. On Anti and Output
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/// edges, this value must not be zero. On Data edges, the value may
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/// be zero, which would mean that no specific register is associated
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/// with this edge.
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void setReg(unsigned Reg) {
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assert((getKind() == Data || getKind() == Anti || getKind() == Output) &&
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"setReg called on non-register dependence edge!");
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assert((getKind() != Anti || Reg != 0) &&
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"SDep::Anti edge cannot use the zero register!");
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assert((getKind() != Output || Reg != 0) &&
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"SDep::Output edge cannot use the zero register!");
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Contents.Reg = Reg;
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}
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};
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/// SUnit - Scheduling unit. This is a node in the scheduling DAG.
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class SUnit {
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private:
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SDNode *Node; // Representative node.
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MachineInstr *Instr; // Alternatively, a MachineInstr.
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public:
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SUnit *OrigNode; // If not this, the node from which
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// this node was cloned.
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// Preds/Succs - The SUnits before/after us in the graph. The boolean value
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// is true if the edge is a token chain edge, false if it is a value edge.
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SmallVector<SDep, 4> Preds; // All sunit predecessors.
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SmallVector<SDep, 4> Succs; // All sunit successors.
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typedef SmallVector<SDep, 4>::iterator pred_iterator;
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typedef SmallVector<SDep, 4>::iterator succ_iterator;
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typedef SmallVector<SDep, 4>::const_iterator const_pred_iterator;
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typedef SmallVector<SDep, 4>::const_iterator const_succ_iterator;
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unsigned NodeNum; // Entry # of node in the node vector.
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unsigned NodeQueueId; // Queue id of node.
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unsigned short Latency; // Node latency.
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unsigned NumPreds; // # of SDep::Data preds.
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unsigned NumSuccs; // # of SDep::Data sucss.
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unsigned NumPredsLeft; // # of preds not scheduled.
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unsigned NumSuccsLeft; // # of succs not scheduled.
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bool isCall : 1; // Is a function call.
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bool isTwoAddress : 1; // Is a two-address instruction.
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bool isCommutable : 1; // Is a commutable instruction.
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bool hasPhysRegDefs : 1; // Has physreg defs that are being used.
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bool hasPhysRegClobbers : 1; // Has any physreg defs, used or not.
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bool isPending : 1; // True once pending.
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bool isAvailable : 1; // True once available.
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bool isScheduled : 1; // True once scheduled.
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bool isScheduleHigh : 1; // True if preferable to schedule high.
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bool isCloned : 1; // True if this node has been cloned.
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Sched::Preference SchedulingPref; // Scheduling preference.
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SmallVector<MachineInstr*, 4> DbgInstrList; // dbg_values referencing this.
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private:
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bool isDepthCurrent : 1; // True if Depth is current.
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bool isHeightCurrent : 1; // True if Height is current.
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unsigned Depth; // Node depth.
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unsigned Height; // Node height.
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public:
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const TargetRegisterClass *CopyDstRC; // Is a special copy node if not null.
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const TargetRegisterClass *CopySrcRC;
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/// SUnit - Construct an SUnit for pre-regalloc scheduling to represent
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/// an SDNode and any nodes flagged to it.
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SUnit(SDNode *node, unsigned nodenum)
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: Node(node), Instr(0), OrigNode(0), NodeNum(nodenum),
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NodeQueueId(0), Latency(0), NumPreds(0), NumSuccs(0), NumPredsLeft(0),
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NumSuccsLeft(0),
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isCall(false), isTwoAddress(false), isCommutable(false),
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hasPhysRegDefs(false), hasPhysRegClobbers(false),
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isPending(false), isAvailable(false), isScheduled(false),
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isScheduleHigh(false), isCloned(false),
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SchedulingPref(Sched::None),
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isDepthCurrent(false), isHeightCurrent(false), Depth(0), Height(0),
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CopyDstRC(NULL), CopySrcRC(NULL) {}
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/// SUnit - Construct an SUnit for post-regalloc scheduling to represent
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/// a MachineInstr.
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SUnit(MachineInstr *instr, unsigned nodenum)
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: Node(0), Instr(instr), OrigNode(0), NodeNum(nodenum),
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NodeQueueId(0), Latency(0), NumPreds(0), NumSuccs(0), NumPredsLeft(0),
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NumSuccsLeft(0),
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isCall(false), isTwoAddress(false), isCommutable(false),
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hasPhysRegDefs(false), hasPhysRegClobbers(false),
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isPending(false), isAvailable(false), isScheduled(false),
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isScheduleHigh(false), isCloned(false),
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SchedulingPref(Sched::None),
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isDepthCurrent(false), isHeightCurrent(false), Depth(0), Height(0),
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CopyDstRC(NULL), CopySrcRC(NULL) {}
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/// SUnit - Construct a placeholder SUnit.
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SUnit()
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: Node(0), Instr(0), OrigNode(0), NodeNum(~0u),
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NodeQueueId(0), Latency(0), NumPreds(0), NumSuccs(0), NumPredsLeft(0),
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NumSuccsLeft(0),
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isCall(false), isTwoAddress(false), isCommutable(false),
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hasPhysRegDefs(false), hasPhysRegClobbers(false),
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isPending(false), isAvailable(false), isScheduled(false),
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isScheduleHigh(false), isCloned(false),
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SchedulingPref(Sched::None),
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isDepthCurrent(false), isHeightCurrent(false), Depth(0), Height(0),
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CopyDstRC(NULL), CopySrcRC(NULL) {}
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/// setNode - Assign the representative SDNode for this SUnit.
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/// This may be used during pre-regalloc scheduling.
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void setNode(SDNode *N) {
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assert(!Instr && "Setting SDNode of SUnit with MachineInstr!");
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Node = N;
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}
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/// getNode - Return the representative SDNode for this SUnit.
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/// This may be used during pre-regalloc scheduling.
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SDNode *getNode() const {
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assert(!Instr && "Reading SDNode of SUnit with MachineInstr!");
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return Node;
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}
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/// setInstr - Assign the instruction for the SUnit.
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/// This may be used during post-regalloc scheduling.
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void setInstr(MachineInstr *MI) {
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assert(!Node && "Setting MachineInstr of SUnit with SDNode!");
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Instr = MI;
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}
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/// getInstr - Return the representative MachineInstr for this SUnit.
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/// This may be used during post-regalloc scheduling.
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MachineInstr *getInstr() const {
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assert(!Node && "Reading MachineInstr of SUnit with SDNode!");
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return Instr;
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}
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/// addPred - This adds the specified edge as a pred of the current node if
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/// not already. It also adds the current node as a successor of the
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/// specified node.
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void addPred(const SDep &D);
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/// removePred - This removes the specified edge as a pred of the current
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/// node if it exists. It also removes the current node as a successor of
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/// the specified node.
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void removePred(const SDep &D);
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/// getDepth - Return the depth of this node, which is the length of the
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/// maximum path up to any node with has no predecessors.
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unsigned getDepth() const {
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if (!isDepthCurrent)
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const_cast<SUnit *>(this)->ComputeDepth();
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return Depth;
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}
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/// getHeight - Return the height of this node, which is the length of the
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/// maximum path down to any node with has no successors.
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unsigned getHeight() const {
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if (!isHeightCurrent)
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const_cast<SUnit *>(this)->ComputeHeight();
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return Height;
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}
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/// setDepthToAtLeast - If NewDepth is greater than this node's
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/// depth value, set it to be the new depth value. This also
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/// recursively marks successor nodes dirty.
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void setDepthToAtLeast(unsigned NewDepth);
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/// setDepthToAtLeast - If NewDepth is greater than this node's
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/// depth value, set it to be the new height value. This also
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/// recursively marks predecessor nodes dirty.
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void setHeightToAtLeast(unsigned NewHeight);
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/// setDepthDirty - Set a flag in this node to indicate that its
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/// stored Depth value will require recomputation the next time
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/// getDepth() is called.
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void setDepthDirty();
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/// setHeightDirty - Set a flag in this node to indicate that its
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/// stored Height value will require recomputation the next time
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/// getHeight() is called.
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void setHeightDirty();
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/// isPred - Test if node N is a predecessor of this node.
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bool isPred(SUnit *N) {
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for (unsigned i = 0, e = (unsigned)Preds.size(); i != e; ++i)
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if (Preds[i].getSUnit() == N)
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return true;
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return false;
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}
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/// isSucc - Test if node N is a successor of this node.
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bool isSucc(SUnit *N) {
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for (unsigned i = 0, e = (unsigned)Succs.size(); i != e; ++i)
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if (Succs[i].getSUnit() == N)
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return true;
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return false;
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}
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void dump(const ScheduleDAG *G) const;
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void dumpAll(const ScheduleDAG *G) const;
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void print(raw_ostream &O, const ScheduleDAG *G) const;
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private:
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void ComputeDepth();
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void ComputeHeight();
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};
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//===--------------------------------------------------------------------===//
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/// SchedulingPriorityQueue - This interface is used to plug different
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/// priorities computation algorithms into the list scheduler. It implements
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/// the interface of a standard priority queue, where nodes are inserted in
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/// arbitrary order and returned in priority order. The computation of the
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/// priority and the representation of the queue are totally up to the
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/// implementation to decide.
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///
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class SchedulingPriorityQueue {
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unsigned CurCycle;
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public:
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SchedulingPriorityQueue() : CurCycle(0) {}
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virtual ~SchedulingPriorityQueue() {}
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virtual void initNodes(std::vector<SUnit> &SUnits) = 0;
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virtual void addNode(const SUnit *SU) = 0;
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virtual void updateNode(const SUnit *SU) = 0;
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virtual void releaseState() = 0;
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virtual bool empty() const = 0;
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virtual void push(SUnit *U) = 0;
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void push_all(const std::vector<SUnit *> &Nodes) {
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for (std::vector<SUnit *>::const_iterator I = Nodes.begin(),
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E = Nodes.end(); I != E; ++I)
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push(*I);
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}
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virtual SUnit *pop() = 0;
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virtual void remove(SUnit *SU) = 0;
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/// ScheduledNode - As each node is scheduled, this method is invoked. This
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/// allows the priority function to adjust the priority of related
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/// unscheduled nodes, for example.
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///
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virtual void ScheduledNode(SUnit *) {}
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virtual void UnscheduledNode(SUnit *) {}
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void setCurCycle(unsigned Cycle) {
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CurCycle = Cycle;
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}
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unsigned getCurCycle() const {
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return CurCycle;
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}
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};
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class ScheduleDAG {
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public:
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MachineBasicBlock *BB; // The block in which to insert instructions
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MachineBasicBlock::iterator InsertPos;// The position to insert instructions
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const TargetMachine &TM; // Target processor
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const TargetInstrInfo *TII; // Target instruction information
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const TargetRegisterInfo *TRI; // Target processor register info
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MachineFunction &MF; // Machine function
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MachineRegisterInfo &MRI; // Virtual/real register map
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std::vector<SUnit*> Sequence; // The schedule. Null SUnit*'s
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// represent noop instructions.
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std::vector<SUnit> SUnits; // The scheduling units.
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SUnit EntrySU; // Special node for the region entry.
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SUnit ExitSU; // Special node for the region exit.
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explicit ScheduleDAG(MachineFunction &mf);
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virtual ~ScheduleDAG();
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/// viewGraph - Pop up a GraphViz/gv window with the ScheduleDAG rendered
|
|
/// using 'dot'.
|
|
///
|
|
void viewGraph();
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|
|
|
/// EmitSchedule - Insert MachineInstrs into the MachineBasicBlock
|
|
/// according to the order specified in Sequence.
|
|
///
|
|
virtual MachineBasicBlock *EmitSchedule() = 0;
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|
|
|
void dumpSchedule() const;
|
|
|
|
virtual void dumpNode(const SUnit *SU) const = 0;
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|
|
|
/// getGraphNodeLabel - Return a label for an SUnit node in a visualization
|
|
/// of the ScheduleDAG.
|
|
virtual std::string getGraphNodeLabel(const SUnit *SU) const = 0;
|
|
|
|
/// addCustomGraphFeatures - Add custom features for a visualization of
|
|
/// the ScheduleDAG.
|
|
virtual void addCustomGraphFeatures(GraphWriter<ScheduleDAG*> &) const {}
|
|
|
|
#ifndef NDEBUG
|
|
/// VerifySchedule - Verify that all SUnits were scheduled and that
|
|
/// their state is consistent.
|
|
void VerifySchedule(bool isBottomUp);
|
|
#endif
|
|
|
|
protected:
|
|
/// Run - perform scheduling.
|
|
///
|
|
void Run(MachineBasicBlock *bb, MachineBasicBlock::iterator insertPos);
|
|
|
|
/// BuildSchedGraph - Build SUnits and set up their Preds and Succs
|
|
/// to form the scheduling dependency graph.
|
|
///
|
|
virtual void BuildSchedGraph(AliasAnalysis *AA) = 0;
|
|
|
|
/// ComputeLatency - Compute node latency.
|
|
///
|
|
virtual void ComputeLatency(SUnit *SU) = 0;
|
|
|
|
/// ComputeOperandLatency - Override dependence edge latency using
|
|
/// operand use/def information
|
|
///
|
|
virtual void ComputeOperandLatency(SUnit *, SUnit *,
|
|
SDep&) const { }
|
|
|
|
/// Schedule - Order nodes according to selected style, filling
|
|
/// in the Sequence member.
|
|
///
|
|
virtual void Schedule() = 0;
|
|
|
|
/// ForceUnitLatencies - Return true if all scheduling edges should be given
|
|
/// a latency value of one. The default is to return false; schedulers may
|
|
/// override this as needed.
|
|
virtual bool ForceUnitLatencies() const { return false; }
|
|
|
|
/// EmitNoop - Emit a noop instruction.
|
|
///
|
|
void EmitNoop();
|
|
|
|
void EmitPhysRegCopy(SUnit *SU, DenseMap<SUnit*, unsigned> &VRBaseMap);
|
|
};
|
|
|
|
class SUnitIterator : public std::iterator<std::forward_iterator_tag,
|
|
SUnit, ptrdiff_t> {
|
|
SUnit *Node;
|
|
unsigned Operand;
|
|
|
|
SUnitIterator(SUnit *N, unsigned Op) : Node(N), Operand(Op) {}
|
|
public:
|
|
bool operator==(const SUnitIterator& x) const {
|
|
return Operand == x.Operand;
|
|
}
|
|
bool operator!=(const SUnitIterator& x) const { return !operator==(x); }
|
|
|
|
const SUnitIterator &operator=(const SUnitIterator &I) {
|
|
assert(I.Node==Node && "Cannot assign iterators to two different nodes!");
|
|
Operand = I.Operand;
|
|
return *this;
|
|
}
|
|
|
|
pointer operator*() const {
|
|
return Node->Preds[Operand].getSUnit();
|
|
}
|
|
pointer operator->() const { return operator*(); }
|
|
|
|
SUnitIterator& operator++() { // Preincrement
|
|
++Operand;
|
|
return *this;
|
|
}
|
|
SUnitIterator operator++(int) { // Postincrement
|
|
SUnitIterator tmp = *this; ++*this; return tmp;
|
|
}
|
|
|
|
static SUnitIterator begin(SUnit *N) { return SUnitIterator(N, 0); }
|
|
static SUnitIterator end (SUnit *N) {
|
|
return SUnitIterator(N, (unsigned)N->Preds.size());
|
|
}
|
|
|
|
unsigned getOperand() const { return Operand; }
|
|
const SUnit *getNode() const { return Node; }
|
|
/// isCtrlDep - Test if this is not an SDep::Data dependence.
|
|
bool isCtrlDep() const {
|
|
return getSDep().isCtrl();
|
|
}
|
|
bool isArtificialDep() const {
|
|
return getSDep().isArtificial();
|
|
}
|
|
const SDep &getSDep() const {
|
|
return Node->Preds[Operand];
|
|
}
|
|
};
|
|
|
|
template <> struct GraphTraits<SUnit*> {
|
|
typedef SUnit NodeType;
|
|
typedef SUnitIterator ChildIteratorType;
|
|
static inline NodeType *getEntryNode(SUnit *N) { return N; }
|
|
static inline ChildIteratorType child_begin(NodeType *N) {
|
|
return SUnitIterator::begin(N);
|
|
}
|
|
static inline ChildIteratorType child_end(NodeType *N) {
|
|
return SUnitIterator::end(N);
|
|
}
|
|
};
|
|
|
|
template <> struct GraphTraits<ScheduleDAG*> : public GraphTraits<SUnit*> {
|
|
typedef std::vector<SUnit>::iterator nodes_iterator;
|
|
static nodes_iterator nodes_begin(ScheduleDAG *G) {
|
|
return G->SUnits.begin();
|
|
}
|
|
static nodes_iterator nodes_end(ScheduleDAG *G) {
|
|
return G->SUnits.end();
|
|
}
|
|
};
|
|
|
|
/// ScheduleDAGTopologicalSort is a class that computes a topological
|
|
/// ordering for SUnits and provides methods for dynamically updating
|
|
/// the ordering as new edges are added.
|
|
///
|
|
/// This allows a very fast implementation of IsReachable, for example.
|
|
///
|
|
class ScheduleDAGTopologicalSort {
|
|
/// SUnits - A reference to the ScheduleDAG's SUnits.
|
|
std::vector<SUnit> &SUnits;
|
|
|
|
/// Index2Node - Maps topological index to the node number.
|
|
std::vector<int> Index2Node;
|
|
/// Node2Index - Maps the node number to its topological index.
|
|
std::vector<int> Node2Index;
|
|
/// Visited - a set of nodes visited during a DFS traversal.
|
|
BitVector Visited;
|
|
|
|
/// DFS - make a DFS traversal and mark all nodes affected by the
|
|
/// edge insertion. These nodes will later get new topological indexes
|
|
/// by means of the Shift method.
|
|
void DFS(const SUnit *SU, int UpperBound, bool& HasLoop);
|
|
|
|
/// Shift - reassign topological indexes for the nodes in the DAG
|
|
/// to preserve the topological ordering.
|
|
void Shift(BitVector& Visited, int LowerBound, int UpperBound);
|
|
|
|
/// Allocate - assign the topological index to the node n.
|
|
void Allocate(int n, int index);
|
|
|
|
public:
|
|
explicit ScheduleDAGTopologicalSort(std::vector<SUnit> &SUnits);
|
|
|
|
/// InitDAGTopologicalSorting - create the initial topological
|
|
/// ordering from the DAG to be scheduled.
|
|
void InitDAGTopologicalSorting();
|
|
|
|
/// IsReachable - Checks if SU is reachable from TargetSU.
|
|
bool IsReachable(const SUnit *SU, const SUnit *TargetSU);
|
|
|
|
/// WillCreateCycle - Returns true if adding an edge from SU to TargetSU
|
|
/// will create a cycle.
|
|
bool WillCreateCycle(SUnit *SU, SUnit *TargetSU);
|
|
|
|
/// AddPred - Updates the topological ordering to accomodate an edge
|
|
/// to be added from SUnit X to SUnit Y.
|
|
void AddPred(SUnit *Y, SUnit *X);
|
|
|
|
/// RemovePred - Updates the topological ordering to accomodate an
|
|
/// an edge to be removed from the specified node N from the predecessors
|
|
/// of the current node M.
|
|
void RemovePred(SUnit *M, SUnit *N);
|
|
|
|
typedef std::vector<int>::iterator iterator;
|
|
typedef std::vector<int>::const_iterator const_iterator;
|
|
iterator begin() { return Index2Node.begin(); }
|
|
const_iterator begin() const { return Index2Node.begin(); }
|
|
iterator end() { return Index2Node.end(); }
|
|
const_iterator end() const { return Index2Node.end(); }
|
|
|
|
typedef std::vector<int>::reverse_iterator reverse_iterator;
|
|
typedef std::vector<int>::const_reverse_iterator const_reverse_iterator;
|
|
reverse_iterator rbegin() { return Index2Node.rbegin(); }
|
|
const_reverse_iterator rbegin() const { return Index2Node.rbegin(); }
|
|
reverse_iterator rend() { return Index2Node.rend(); }
|
|
const_reverse_iterator rend() const { return Index2Node.rend(); }
|
|
};
|
|
}
|
|
|
|
#endif
|